Abstract: In wireless communications systems, power conservation is important. The communications system anticipates the need to vary the signal strength of transmitting mobile units, and provides that base station with information concerning the direction of the mobile unit relative to the base station which is utilized in handing off the mobile unit from one base station to another.

Abstract: A method, system and computer program product for generating variable price billing whereby a customer may balance its data traffic in response to such billing. A subsystem in an edge gateway may extract the packet header from a copy of a received packet of data associated with a session between a customer and a server and generate a key based on the extracted packet header. The key may be used to index into a table that may store pointers to particular statistics records associated with particular sessions. Once the subsystem identifies the statistics record associated with the current session, the subsystem may execute a per packet statistics update for the statistics record associated with the session. A per packet statistics update may include one or more of the following: time stamping arrival of the packet, updating packet count, updating byte count, determining transfer rate, determining distance packet traveled.

Abstract: A multimedia presentation apparatus and method by which a presenter is freed from the requirement of having or providing or transporting a supporting computer system such as the notebook or laptop system by the incorporation of computing capability and an accessible data port into the housing of the apparatus through which an executable data file may be delivered to cause generation of the desired presentation.

Abstract: A server farm formed by a plurality of computer systems joined together by a network processor which transfers data exchanged with an external network supported by the server farm at a data rate substantially the same as the data flow rate of the network and related method

Abstract: An interface connection is described for joining a host device, such as a Network Processor, to peripherals such as modems, printers, local area networks, Ethernets and Token-Ring interfaces. The connection is particularly useful for joining portable computers, such as laptops, to these peripherals. The connector utilizes a programmable Network Processor (NP) either in the host device or in an external fan-out box. This programmable Network Processor adapts the host device to a variety of peripheral devices utilizing different protocols and I/O speeds. The NP can use a Digital Signal Processor to provide programmable services to the physical layers. The host device may contain a high-speed communication interface with the NP contained in the external connection box.

Abstract: A network processor is used for the routing of objects in non-data networking applications. The processor utilizes the Open Shortest Path First (OSPF) algorithm to capitalize on the benefits of data control for object traffic control and costs. A network processor is used at each point in a grid represented by intersecting paths. One or more routing tables are embedded in each network processor. Each routing table describes links with other network processors in the grid to which the network processor is interconnected. A cost factor is associated with each link and is constantly updated by the OSPF as new information becomes available. If a link or route becomes unavailable, the cost is set at infinity. The system then creates an alternative path for the object between a source and the desired destination that bypasses the unavailable link or route.

Abstract: This invention makes use of the capability of a network processor (as described more fully herein) to perform software directed tree searches. Pattern recognition data processing, as expanded upon in the detailed description, opens possibilities for data mining, virus protection, security and other functions. As realized in accordance with the varying embodiments of this invention, significant performance improvements are obtained and highly scaleable systems are created which are capable of examining large amounts of data, both in real time and in batch modes.

Abstract: A computer system in which a network processor disposed between a central processing unit and supporting peripheral subsystems and among the peripheral subsystems handles addressing of memory space.

Abstract: Vehicles such as airliners or trains can be equipped with a form of local area network in which individual network connections are made to individual passenger seats using standard telephony connectors. Passengers having computers can connect to the network using their own conventional telephone cables. Wireless communications technology is used to link the vehicle network to external ground stations or satellite systems. To meet the DC power requirements of mobile computer users, the vehicle includes a DC power source. A normally unused wire-pair in the telephony connectors brings the DC power to each seatback. A slightly modified connector is used to transfer the DC power to the computer's DC power subsystem.

Abstract: A method and apparatus for multi-protocol LAN support, which is applicable to Ethernet, Token-Ring, and Asynchronous Transfer Mode (ATM) protocols. The LAN support is located at a workstation and provides for automatic determination of the LAN protocol type and speed. A common adapter card is provided for use in the workstation to interface the workstation to any of the LANs of interest. A four-step sequential process is taught for determining the protocol type and speed.

Abstract: An option card, the combination of the option card with a computer system, and a method by which the central processing unit of a computer system can be relieved of the burden of processing protocol bits in a bit stream passing through a digital signal network.

Abstract: A network processor is disclosed. The network processor comprises a plurality of standard cells; and at least one field programmable gate array (FPGA) cell that can communicate with at least one of the standard cells. The at least one FPGA cell can provide a specified function based upon field programming techniques to allow for customization of the network processor. Utilizing a method and system in accordance with the present invention, a network processor can be customized to implement a variety of functions in hardware using embedded FPGA macros. The combined technology of ASIC standard cells plus FPGA cells enables fast time-to-market for new designs while optimizing cost and performance. In addition, the combined ASIC plus FPGA on a single die allows the chip developer to use proven standard cell macros for common logic and programmable cells for high-risk logic.

Abstract: A server farm formed by a plurality of computer systems joined together by a network processor which transfers data exchanged with an external network supported by the server farm at a data rate substantially the same as the data flow rate of the network and related method

Abstract: Methods, apparatus and program products which monitor access points through which data can be exchanged with a network, identify an unauthorized access point, and accumulate charges for network access and usage passing through the unauthorized access point.

Abstract: Methods, apparatus and program products which monitor access points through which data can be exchanged with a network, identify an unauthorized access point, and selectively apply filters to the flow of data through an unauthorized access point.

Abstract: A server farm formed by a plurality of computer systems joined together by a network processor which transfers data exchanged with an external network supported by the server farm at a data rate substantially the same as the data flow rate of the network and related method.

Abstract: An interface connection is described for joining a host device, such as a Network Processor, to peripherals such as modems, printers, local area networks, Ethernets and Token-Ring interfaces. The connection is particularly useful for joining portable computers, such as laptops, to these peripherals. The connector utilizes a programmable Network Processor (NP) either in the host device or in an external fan-out box. This programmable Network Processor adapts the host device to a variety of peripheral devices utilizing different protocols and I/O speeds. The NP can use a Digital Signal Processor to provide programmable services to the physical layers. The host device may contain a high-speed communication interface with the NP contained in the external connection box.

Abstract: A network processor is used for the routing of objects in non-data networking applications. The processor utilizes the Open Shortest Path First (OSPF) algorithm to capitalize on the benefits of data control for object traffic control and costs. A network processor is used at each point in a grid represented by intersecting paths. One or more routing tables are embedded in each network processor. Each routing table describes links with other network processors in the grid to which the network processor is interconnected. A cost factor is associated with each link and is constantly updated by the OSPF as new information becomes available. If a link or route becomes unavailable, the cost is set at infinity. The system then creates an alternative path for the object between a source and the desired destination that bypasses the unavailable link or route.

Abstract: A network processor is disclosed. The network processor comprises a plurality of standard cells; and at least one field programmable gate array (FPGA) cell that can communicate with at least one of the standard cells. The at least one FPGA cell can provide a specified function based upon field programming techniques to allow for customization of the network processor. Utilizing a method and system in accordance with the present invention, a network processor can be customized to implement a variety of functions in hardware using embedded FPGA macros. The combined technology of ASIC standard cells plus FPGA cells enables fast time-to-market for new designs while optimizing cost and performance. In addition, the combined ASIC plus FPGA on a single die allows the chip developer to use proven standard cell macros for common logic and programmable cells for high-risk logic.

Abstract: A Digital Signal Processor (DSP) is integrated within a network processor. The DSP is integrated as a core function and has an analog interface and/or a digital interface. The DSP may receive analog signals and convert them to digital signals which may undergo additional processing within the DSP. The output of the DSP maybe routed by the network processor to physical layer devices. The DSP may also receive digital signals which may be processed by the DSP's specialized operations. The combination network processor and DSP may be easily programmed to implement specialized communication and data handling functions.