Abstract: An integrated circuit (IC) having a link layer that (1) simultaneously receives both hardware debug data from on-chip ASIC logic and software debug data from an on-chip programmable processor and (2) serializes the hardware and software debug data streams to generate one or more serialized debug data streams, e.g., containing both hardware and software debug data, for output to off-chip debug testing equipment to support debug testing of both the ASIC logic and the programmable processor. Cross triggering can be implemented on-chip to support simultaneous display of correlated hardware and software debug information on appropriate monitors. The present invention supports debug testing using external debug testing equipment that does not require a hardware logic analyzer.

Abstract: An integrated circuit (IC) having a link layer that (1) simultaneously receives both hardware debug data from on-chip ASIC logic and software debug data from an on-chip programmable processor and (2) serializes the hardware and software debug data streams to generate one or more serialized debug data streams, e.g., containing both hardware and software debug data, for output to off-chip debug testing equipment to support debug testing of both the ASIC logic and the programmable processor. Cross triggering can be implemented on-chip to support simultaneous display of correlated hardware and software debug information on appropriate monitors. The present invention supports debug testing using external debug testing equipment that does not require a hardware logic analyzer.

Abstract: An optical disc storage system comprises a sliding mode controller for actuating an optical read head assembly over an optical disc during focus capture, focus tracking, track seeking and centerline tracking. The sliding mode controller is a non-linear control system which operates by switching between positive and negative feedback in order to force certain phase states (such as the read head's position error and velocity) to follow a predetermined phase state trajectory. Sliding mode control provides improved compensation to parametric variations, external load disturbances and other transients such as, for example, the focus capture transient. Furthermore, the sliding mode positive and negative feedback gains need only be within a predetermined range, thereby allowing gain values of 2.sup.n which significantly reduces the complexity and cost of the gain multipliers.

Abstract: Methods for addressing a block addressable memory with a Gray code to minimize spurious noise generation and enhance diagnostic operations for data and address bus error detection.

Abstract: A symbol interleaving method for organizing data in a semiconductor memory such that fault tolerance of the memory is optimized when used in conjunction with a Reed-Solomon burst error correcting code. The Reed-Solomon symbols are aligned with respect to the bus bits of the memory such that the impact of a bus bit failure that affects all memory devices in the memory using the bus is constrained within the correction capability of the ECC. The symbols also are distributed among the memory devices in order to maximize fault tolerance. Up to two memory devices in the preferred embodiment may fail without exceeding the correction capability of the code.

Abstract: A primary transceiver having a driver/receiver initially drives a bus while a secondary transceiver having a driver/receiver receives the signals present on the bus. The system compares the signals received by the secondary driver/receiver and the inputs to the primary driver/receiver. If a difference is detected, the system controller disables the primary driver/receiver and enables the secondary driver/receiver which drives the bus.