Patents by Inventor Francis J. Kub

Francis J. Kub has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040009649
    Abstract: A method of bonding a wafer to a substrate comprising the steps of: providing a wafer having a front surface and a back surface; attaching the front surface of the wafer to a support; thinning the wafer from the back surface; bonding the back surface of the wafer to a substrate using a thin bonding technique; and removing the support from the front surface of the wafer. A circuit comprising: a substrate; and a wafer; wherein the wafer is at most about 50 microns thick; wherein the wafer has a front surface comprising features; and wherein the wafer has a back surface bonded to the substrate using a thin bonding technique.
    Type: Application
    Filed: May 20, 2003
    Publication date: January 15, 2004
    Inventors: Francis J. Kub, Karl D. Hobart
  • Publication number: 20030199105
    Abstract: Thin layers of high quality single-crystal piezoelectric material, high temperature sintered piezoelectric material, or high quality thin film grown material are transferred to an appropriate substrate using hydrogen ion implant layer splitting and bonding. The substrate to which the thin piezoelectric material layer is transferred may contain CMOS or GaAs circuitry. When the substrate contains CMOS or GaAs circuitry, the circuitry on the surface of the GaAs or CMOS substrate may be covered with an oxide. The oxide is then planarized using chemical mechanical polishing, and the thin film resonator material is transferred to the GaAs or CMOS circuit using wafer bonding and hydrogen ion layer splitting.
    Type: Application
    Filed: April 22, 2002
    Publication date: October 23, 2003
    Inventors: Francis J. Kub, Karl D. Hobart
  • Publication number: 20030186521
    Abstract: A method for making devices having either a substrate with CMOS or GaAs circuitry or which is optimized for a particular property is provided. In one alternative, a film layer of thin film functional material is grown on a large diameter growth substrate. One or more protective layers may be deposited on the surface of the growth substrate before the thin film functional material is deposited. Hydrogen is implanted to a selected depth within the growth substrate or within a protective layer to form a hydrogen ion layer. The growth substrate and associated layers are bonded to a second substrate. The layers are split along the hydrogen ion implant and the portion of the growth substrate and associated layer that is on the side of the ion layer away from the second substrate is removed.
    Type: Application
    Filed: March 29, 2002
    Publication date: October 2, 2003
    Inventors: Francis J. Kub, Karl D. Hobart
  • Patent number: 6607969
    Abstract: A method for making a thin film device or pyroelectric sensor is provided. A film layer of thin film functional material is grown on a large diameter growth substrate. One or more protective layers may be deposited on the surface of the growth substrate before the thin film functional material is deposited. Hydrogen is implanted to a selected depth within the growth substrate or within a protective layer to form a hydrogen ion layer. The growth substrate and associated layers are bonded to a second substrate. The layers are split along the hydrogen ion implant and the portion of the growth substrate and associated layers that are on the side of the ion layer away from the second substrate are removed.
    Type: Grant
    Filed: March 18, 2002
    Date of Patent: August 19, 2003
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Karl D. Hobart
  • Patent number: 6593212
    Abstract: A method is provided for transferring an electro-optical layer grown on a growth substrate to a handle substrate. The method includes implanting hydrogen ions in the transfer substrate to form an intermediate hydrogen ion implant layer and bonding the transfer substrate to the handle substrate to form a joined structure. The joined structure is heated to a temperature sufficient to split the joined structure to thereby transfer a portion of the electro-optical layer to the handle substrate.
    Type: Grant
    Filed: October 29, 2001
    Date of Patent: July 15, 2003
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Karl D. Hobart
  • Patent number: 6555451
    Abstract: A method is provided for making ultra-shallow diffused junctions using an elemental dopant. A semiconductor wafer is cleaned for providing a clean reaction surface. The cleaned wafer in loaded onto a stage located in a doping system. A quantity of elemental dopant atoms are placed in a partially enclosed elemental dopant source which is within a secondary vacuum enclosure. A quantity of the elemental dopant atoms having thermal velocities are deposited onto a surface of the wafer, and the wafer is heated for diffusing the elemental dopant into the wafer. In one embodiment, the heating is conducted by heating the wafer in ultra-high vacuum for diffusing the portion of the doping atoms into the wafer, and the deposition and heating occur simultaneously. In another embodiment, the surface of the wafer is hydrogen terminated, the wafer is removed from the UHV system, and the heating of the wafer is conducted outside of the UHV system by heating the wafer in a furnace.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: April 29, 2003
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Karl D. Hobart
  • Publication number: 20030064535
    Abstract: A method for manufacturing an electronic device utilizing a thin GaN material is provided in which a GaN layer is epitaxially grown on a transfer substrate. A hydrogen ion implant layer is formed in the GaN layer. A handle substrate having desirable thermal or electrical conductivity is bonded to the transfer substrate having the GaN layer grown thereon. The joined structure is heated to split off the transfer substrate along the hydrogen ion implant layer, thereby resulting in an optimized substrate with GaN layer transferred thereto.
    Type: Application
    Filed: September 28, 2001
    Publication date: April 3, 2003
    Inventors: Francis J. Kub, Karl D. Hobart
  • Patent number: 6497763
    Abstract: A method for making a multilayered electronic device with at least one epitaxial layer grown on a single-crystal film bonded to a composite wherein at least one layer is polycrystalline, the method includes the step of bonding a single-crystal film at least one of the epitaxial layers on the single-crystal film wherein thermal coefficients of expansion for the substrate and the epitaxial layer are closely matched.
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: December 24, 2002
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Karl D. Hobart
  • Patent number: 6448909
    Abstract: An analog continuous wavelet transform circuit is implemented using a bank of quadrature voltage controlled oscillators (VCOs) and a bank of synchronous receivers. The synchronous receivers act as a bandpass filter bank, the center frequency of each synchronous receiver bandpass filter being set by the frequency of a corresponding VCO. Each quadrature VCO generates differential in-phase. (I) and quadrature (Q) outputs, and has a multiplier, gain amplifier/low-pass filter, and a squarer for both I and Q phases, and the squarer outputs are summed to produce the synchronous receiver output. Each synchronous receiver output represents the instantaneous input signal power within a specific bandpass filter bandwidth filter. The center frequency of the bandpass filter is determined by the VCO frequency, and the bandpass filter bandwidth is set by the synchronous receiver low-pass filter bandwidth.
    Type: Grant
    Filed: January 8, 2001
    Date of Patent: September 10, 2002
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Eric D. Justh
  • Publication number: 20020096106
    Abstract: A method for making a multilayered electronic device with at least one epitaxial layer grown on a single-crystal film bonded to a composite wherein at least one layer is polycrystalline, the method includes the step of bonding a single-crystal film at least one of the epitaxial layers on the single-crystal film wherein thermal coefficients of expansion for the substrate and the epitaxial layer are closely matched.
    Type: Application
    Filed: January 19, 2001
    Publication date: July 25, 2002
    Inventors: Francis J. Kub, Karl D. Hobart
  • Publication number: 20020032570
    Abstract: An analog continuous wavelet transform circuit is implemented using a bank of quadrature voltage controlled oscillators (VCOs) and a bank of synchronous receivers. The synchronous receivers act as a bandpass filter bank, the center frequency of each synchronous receiver bandpass filter being set by the frequency of a corresponding VCO. Each quadrature VCO generates differential in-phase (I) and quadrature (Q) outputs, and has a multiplier, gain amplifier/low-pass filter, and a squarer for both I and Q phases, and the squarer outputs are summed to produce the synchronous receiver output. Each synchronous receiver output represents the instantaneous input signal power within a specific bandpass filter bandwidth filter. The center frequency of the bandpass filter is determined by the VCO frequency, and the bandpass filter bandwidth is set by the synchronous receiver low-pass filter bandwidth.
    Type: Application
    Filed: January 8, 2001
    Publication date: March 14, 2002
    Inventors: Francis J. Kub, Eric D. Justh
  • Patent number: 6328796
    Abstract: A method for making a multilayered structure with a single crystal film bonded to a polycrystalline substrate has the steps of: bonding a single crystal film to a polycrystalline substrate; and growing an epitaxial layer on said single crystal film bonded to said polycrystalline substrate.
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: December 11, 2001
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Karl D. Hobart
  • Patent number: 6323108
    Abstract: The invention uses implantation, typically hydrogen implantation or implantation of hydrogen in combination with other elements, to a selected depth into a wafer with that contains one or more etch stops layers, treatment to split the wafer at this selected depth, and subsequent etching procedures to expose etch stop layer and ultra-thin material layer. A method for making an ultra-thin material layer bonded to a substrate, has the steps: (a) growing an etch stop layer on a first substrate; (b) growing an ultra-thin material layer on the etch stop layer; (c) implanting an implant gas to a selected depth into the first substrate; (d) bonding the ultra-thin material layer to a second substrate; (e) treating the first substrate to cause the first substrate to split at the selected depth; (f) etching remaining portion of first substrate to expose the etch stop layer, and (g) etching the etch stop layer to expose the ultra-thin material layer.
    Type: Grant
    Filed: July 27, 1999
    Date of Patent: November 27, 2001
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Karl D. Hobart
  • Patent number: 6274892
    Abstract: One embodiment of a semiconductor device includes a laterally extending semiconductor base, a buffer adjacent the base and having a first conductivity type dopant, and a laterally extending emitter adjacent the buffer and opposite the base and having a second conductivity type dopant. The buffer is relatively thin and has a first conductivity type dopant concentration greater than a second conductivity type dopant concentration in adjacent emitter portions to provide a negative temperature coefficient for current gain and a positive temperature coefficient for forward voltage for the device. The buffer may be silicon or germanium. A low temperature bonded interface may be between the emitter and the buffer or the buffer and the base. Another embodiment of a device may include a laterally extending localized lifetime killing portion between oppositely doped first and second laterally extending portions.
    Type: Grant
    Filed: March 9, 1998
    Date of Patent: August 14, 2001
    Assignee: Intersil Americas Inc.
    Inventors: Francis J. Kub, Victor Temple, Karl Hobart, John Neilson
  • Patent number: 6242324
    Abstract: An aspect of the present invention is a method for making a functional active device (photodetector, laser, LED, optical modulator, optical switch, field effect transistor, MOSFET, MODFET, high electron mobility transistor, heterojunction bipolar transistor, resonant tunneling device, Esaki tunneling device etc.) disposed over a complementary metal oxide semiconductor (CMOS) device, having the steps; (a) forming an ultrathin compliant layer direct bonded to an oxide layer over said-CMOS device; (b) growing an epitaxial layer on said ultra-thin compliant layer (c) forming a functional active device in said epitaxial layer grown on said epitaxial layer that is grown on said ultrathin compliant layer; and (c) interconnecting said functional active device and said CMOS device, wherein said CMOS device is configured as either a readout circuit or a control circuit for said photodetector.
    Type: Grant
    Filed: August 10, 1999
    Date of Patent: June 5, 2001
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Karl D. Hobart
  • Patent number: 6201342
    Abstract: An electron emitting device characterized by a monocrystalline substrate, a plurality of monocrystalline nanomesas or pillars disposed on the substrate in a spaced relationship and extending generally normally therefrom, monocrystalline self-assembled tips disposed on top of the nanomesas, and essentially atomically sharp apexes on the tips for field emitting electrons. A method for making the emitters is characterized by forming a gate electrode and gate electrode apertures before forming the tips on the nanomesas.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: March 13, 2001
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Karl D. Hobart, Francis J. Kub, Henry F. Gray, Mark E. Twigg, Phillip E. Thompson, Jonathan Shaw
  • Patent number: 6194290
    Abstract: A method for making at least one semiconductor power device with current conduction in a vertical direction from a plurality of semiconductor substrates includes processing at least one surface of each of two semiconductor substrates to form at least one of a metal layer and a doped region. The substrates are bonded together so that the at least one processed surface of each of the two semiconductor substrates define outer surfaces of the semiconductor device. The method further includes annealing the bonded together substrates at an anneal temperature so as to not adversely effect the processed surfaces. The method allows the making of a double sided semiconductor power device with a reduction in the number of sequential processing steps. The direct bonding approach allows current production recipes for fabricating single sided power devices to be used without requiring a separate process sequence.
    Type: Grant
    Filed: March 9, 1998
    Date of Patent: February 27, 2001
    Assignee: Intersil Corporation
    Inventors: Francis J. Kub, Victor Temple, Karl Hobart, John Neilson
  • Patent number: 6153495
    Abstract: A method for making a semiconductor device from a plurality of semiconductor substrates includes the steps of: processing at least one surface of at least one of the substrates; thinning at least one of the substrates; bonding the processed and thinned substrates together so that the at least one processed surface defines an outer surface of the semiconductor device; and annealing the bonded together substrates at a relatively low anneal temperature so as to not adversely effect the at least one processed surface. The step of thinning preferably comprises removing a surface portion of the least one substrate opposite the processed surface, to a thickness of less than about 200 .mu.m. A gettering layer may be formed for the at least one substrate prior to thinning. Accordingly, the step of thinning removes the gettering layer. An implanted region may be formed at a surface of the at least one substrate opposite the processed surface prior to bonding.
    Type: Grant
    Filed: March 9, 1998
    Date of Patent: November 28, 2000
    Assignee: Intersil Corporation
    Inventors: Francis J. Kub, Victor Temple, Karl Hobart, John Neilson
  • Patent number: 6113451
    Abstract: An electron emitting device characterized by a monocrystalline substrate, a plurality of monocrystalline nanomesas or pillars disposed on the subste in a spaced relationship and extending generally normally therefrom, monocrystalline self-assembled tips disposed on top of the nanomesas, and essentially atomically sharp apexes on the tips for field emitting electrons. A method for making the emitters is characterized by forming a gate electrode and gate electrode apertures before forming the tips on the nanomesas.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: September 5, 2000
    Assignee: The United State of America as represented by the Secretary of the Navy
    Inventors: Karl D. Hobart, Francis J. Kub, Henry F. Gray, Mark E. Twigg, Phillip E. Thompson, Jonathan Shaw
  • Patent number: H1883
    Abstract: A continuous-time multiplier-integrator-multiplier circuit in which the integrator is a transconductance-C circuit. This permits the integrators to have long time constants despite being tightly fabricated on an integrated semiconductor chip. The multipliers can preferably be Gilbert multipliers, to improve circuit frequency response.
    Type: Grant
    Filed: December 3, 1992
    Date of Patent: October 3, 2000
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Eric W. Justh