Patents by Inventor Francis J. Morris
Francis J. Morris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9373460Abstract: Systems and methods for providing high-capacitive RF MEMS switches are provided. In one embodiment, the invention relates to a micro-electro-mechanical switch assembly including a substrate, an electrode disposed on a portion of the substrate, a dielectric layer disposed on at least a portion of the electrode, a metal layer disposed on at least a portion of the dielectric layer, and a flexible membrane having first and second ends supported at spaced locations on the substrate base, where the flexible membrane is configured to move from a default position to an actuated position in response to a preselected switching voltage applied between the flexible membrane and the electrode, and where, in the actuated position, the flexible membrane is in electrical contact with the metal layer.Type: GrantFiled: December 26, 2012Date of Patent: June 21, 2016Assignee: RAYTHEON COMPANYInventors: Brandon W. Pillans, Francis J. Morris, Mikel J. White
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Patent number: 9281128Abstract: A switchable capacitor having: a dielectric; a pair of electrodes, a first one of the electrodes having the dielectric thereon and a second, flexible one of the electrodes being suspended over the dielectric when the switchable capacitor is in an de-activated state; and top plate disposed between the dielectric and the second, flexible electrode and connected to a reference potential. When the switchable capacitor is electrostatically driven to an activated state, the second one of the electrodes contacts the top plate and when the switchable capacitor is returned to the de-activated state, charge on the top plate is discharged to the reference potential.Type: GrantFiled: July 24, 2012Date of Patent: March 8, 2016Assignee: Raytheon CompanyInventors: Francis J. Morris, Cody B. Moody, Andrew Malczewski
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Patent number: 9269497Abstract: A switchable capacitor including a first electrode, a dielectric layer on the first electrode, a second electrode configured to be suspended in an undeflected position over the dielectric layer in a de-activated state, and to deflect toward the first electrode in an activated state in response to a voltage difference between the two electrodes, a gap between the second electrode and the dielectric layer in the activated state being less than a corresponding gap in the de-activated state, and a capacitor having a first and second end, coupled to one of the electrodes at the first end, and configured to reduce the voltage difference between the electrodes as the second electrode deflects toward the first electrode in the activated state, wherein the voltage difference between the electrodes corresponds to a bias voltage applied across the second end of the capacitor and an other one of the first and second electrodes.Type: GrantFiled: May 30, 2014Date of Patent: February 23, 2016Assignee: RAYTHEON COMPANYInventor: Francis J. Morris
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Publication number: 20150348714Abstract: A switchable capacitor including a first electrode, a dielectric layer on the first electrode, a second electrode configured to be suspended in an undeflected position over the dielectric layer in a de-activated state, and to deflect toward the first electrode in an activated state in response to a voltage difference between the two electrodes, a gap between the second electrode and the dielectric layer in the activated state being less than a corresponding gap in the de-activated state, and a capacitor having a first and second end, coupled to one of the electrodes at the first end, and configured to reduce the voltage difference between the electrodes as the second electrode deflects toward the first electrode in the activated state, wherein the voltage difference between the electrodes corresponds to a bias voltage applied across the second end of the capacitor and an other one of the first and second electrodes.Type: ApplicationFiled: May 30, 2014Publication date: December 3, 2015Applicant: Raytheon CompanyInventor: Francis J. Morris
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Patent number: 9142429Abstract: A method for forming an integrated circuit includes transforming at least a portion of a first substrate layer to form a conductive region within the first substrate layer. An integrated circuit device is provided proximate an outer surface of the first substrate layer. The integrated circuit device transmits or receives electrical signals through the conductive region. A second substrate layer is disposed proximate to the outer surface of the first substrate layer to enclose the integrated circuit device in a hermetic environment.Type: GrantFiled: June 23, 2014Date of Patent: September 22, 2015Assignee: RAYTHEON COMPANYInventors: Premjeet Chahal, Francis J. Morris
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Publication number: 20140299966Abstract: A method for forming an integrated circuit includes transforming at least a portion of a first substrate layer to form a conductive region within the first substrate layer. An integrated circuit device is provided proximate an outer surface of the first substrate layer. The integrated circuit device transmits or receives electrical signals through the conductive region. A second substrate layer is disposed proximate to the outer surface of the first substrate layer to enclose the integrated circuit device in a hermetic environment.Type: ApplicationFiled: June 23, 2014Publication date: October 9, 2014Inventors: Premjeet Chahal, Francis J. Morris
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Patent number: 8803314Abstract: A method for forming an integrated circuit includes transforming at least a portion of a first substrate layer to form a conductive region within the first substrate layer. An integrated circuit device is provided proximate an outer surface of the first substrate layer. The integrated circuit device transmits or receives electrical signals through the conductive region. A second substrate layer is disposed proximate to the outer surface of the first substrate layer to enclose the integrated circuit device in a hermetic environment.Type: GrantFiled: December 14, 2012Date of Patent: August 12, 2014Assignee: Raytheon CompanyInventors: Premjeet Chahal, Francis J. Morris
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Publication number: 20140028113Abstract: A switchable capacitor having: a dielectric; a pair of electrodes, a first one of the electrodes having the dielectric thereon and a second, flexible one of the electrodes being suspended over the dielectric when the switchable capacitor is in an de-activated state; and top plate disposed between the dielectric and the second, flexible electrode and connected to a reference potential. When the switchable capacitor is electrostatically driven to an activated state, the second one of the electrodes contacts the top plate and when the switchable capacitor is returned to the de-activated state, charge on the top plate is discharged to the reference potential.Type: ApplicationFiled: July 24, 2012Publication date: January 30, 2014Applicant: Raytheon CompanyInventors: Francis J. Morris, Cody B. Moody, Andrew Malczewski
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Patent number: 8535797Abstract: In accordance with the teachings of one embodiment of the present disclosure, a method of forming high-density metal interconnects on flexible, thin-film plastic includes laminating a dry photoresist layer to a substrate. The photoresist-laminated substrate is baked. An assembly is formed by laminating a plastic film to the baked, photoresist-laminated substrate. One or more electrically conductive interconnect layers are processed on a first surface of the laminated plastic film. The processing of the one or more electrically conductive interconnects includes photolithography. The assembly is baked and soaked in a liquid. The processed plastic film is then separated from the substrate.Type: GrantFiled: January 13, 2012Date of Patent: September 17, 2013Assignee: Raytheon CompanyInventor: Francis J. Morris
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Patent number: 8368491Abstract: Systems and methods for providing high-capacitive RF MEMS switches are provided. In one embodiment, the invention relates to a micro-electro-mechanical switch assembly including a substrate, an electrode disposed on a portion of the substrate, a dielectric layer disposed on at least a portion of the electrode, a metal layer disposed on at least a portion of the dielectric layer, and a flexible membrane having first and second ends supported at spaced locations on the substrate base, where the flexible membrane is configured to move from a default position to an actuated position in response to a preselected switching voltage applied between the flexible membrane and the electrode, and where, in the actuated position, the flexible membrane is in electrical contact with the metal layer.Type: GrantFiled: April 22, 2010Date of Patent: February 5, 2013Assignee: Raytheon CompanyInventors: Brandon W. Pillans, Francis J. Morris, Mikel J. White
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Patent number: 8343806Abstract: A method for forming an integrated circuit includes transforming at least a portion of a first substrate layer to form a conductive region within the first substrate layer. An integrated circuit device is provided proximate an outer surface of the first substrate layer. The integrated circuit device transmits or receives electrical signals through the conductive region. A second substrate layer is disposed proximate to the outer surface of the first substrate layer to enclose the integrated circuit device in a hermetic environment.Type: GrantFiled: March 5, 2009Date of Patent: January 1, 2013Assignee: Raytheon CompanyInventors: Premjeet Chahal, Francis J. Morris
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Publication number: 20120261168Abstract: In accordance with the teachings of one embodiment of the present disclosure, a method of forming high-density metal interconnects on flexible, thin-film plastic includes laminating a dry photoresist layer to a substrate. The photoresist-laminated substrate is baked. An assembly is formed by laminating a plastic film to the baked, photoresist-laminated substrate. One or more electrically conductive interconnect layers are processed on a first surface of the laminated plastic film. The processing of the one or more electrically conductive interconnects includes photolithography. The assembly is baked and soaked in a liquid. The processed plastic film is then separated from the substrate.Type: ApplicationFiled: January 13, 2012Publication date: October 18, 2012Applicant: RAYTHEON COMPANYInventor: Francis J. Morris
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Patent number: 8114576Abstract: In accordance with the teachings of one embodiment of the present disclosure, a method of forming high-density metal interconnects on flexible, thin-film plastic includes laminating a dry photoresist layer to a substrate. The photoresist-laminated substrate is baked. An assembly is formed by laminating a plastic film to the baked, photoresist-laminated substrate. One or more electrically conductive interconnect layers are processed on a first surface of the laminated plastic film. The processing of the one or more electrically conductive interconnects includes photolithography. The assembly is baked and soaked in a liquid. The processed plastic film is then separated from the substrate.Type: GrantFiled: February 29, 2008Date of Patent: February 14, 2012Assignee: Raytheon CompanyInventor: Francis J. Morris
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Publication number: 20110259717Abstract: Systems and methods for providing high-capacitive RF MEMS switches are provided. In one embodiment, the invention relates to a micro-electro-mechanical switch assembly including a substrate, an electrode disposed on a portion of the substrate, a dielectric layer disposed on at least a portion of the electrode, a metal layer disposed on at least a portion of the dielectric layer, and a flexible membrane having first and second ends supported at spaced locations on the substrate base, where the flexible membrane is configured to move from a default position to an actuated position in response to a preselected switching voltage applied between the flexible membrane and the electrode, and where, in the actuated position, the flexible membrane is in electrical contact with the metal layer.Type: ApplicationFiled: April 22, 2010Publication date: October 27, 2011Inventors: Brandon W. PILLANS, Francis J. MORRIS, Mikel J. WHITE
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Patent number: 7859658Abstract: A polarizing filter includes a portion with a filtering layer having a plurality of openings extending therethrough, where this portion has a maximum physical thickness in a radiation travel direction which is less than approximately one wavelength of the radiation being filtered. A method of making the filter includes: forming a filtering layer over a substrate; creating a plurality of openings through a portion of the filtering layer; and separating the filtering layer from the substrate.Type: GrantFiled: August 28, 2006Date of Patent: December 28, 2010Assignee: Raytheon CompanyInventors: Premjeet Chahal, Francis J. Morris
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Publication number: 20100224980Abstract: A method for forming an integrated circuit includes transforming at least a portion of a first substrate layer to form a conductive region within the first substrate layer. An integrated circuit device is provided proximate an outer surface of the first substrate layer. The integrated circuit device transmits or receives electrical signals through the conductive region. A second substrate layer is disposed proximate to the outer surface of the first substrate layer to enclose the integrated circuit device in a hermetic environment.Type: ApplicationFiled: March 5, 2009Publication date: September 9, 2010Applicant: Raytheon CompanyInventors: Premjeet Chahal, Francis J. Morris
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Patent number: 7474171Abstract: A Micro-Electro-Mechanical system (MEMS) device includes a doped semiconductor layer that is disposed outwardly from a substrate. The MEMS device further includes an insulation layer that is disposed outwardly from and in contact with the doped semiconductor layer. The MEMS device also includes a conductive membrane that is disposed outwardly from the insulation layer by a distance that defines an air gap between the conductive membrane and the insulation layer. The conductive membrane is operable to come in contact with the insulation layer when an appropriate voltage is applied between the conductive membrane and the doped semiconductor layer. In one particular embodiment, the combination of the doped semiconductor layer and the insulation layer operates to provide a path to dissipate any excess electrical charge received by the insulation layer.Type: GrantFiled: June 1, 2005Date of Patent: January 6, 2009Assignee: Raytheon CompanyInventor: Francis J. Morris
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Publication number: 20080213678Abstract: In accordance with the teachings of one embodiment of the present disclosure, a method of forming high-density metal interconnects on flexible, thin-film plastic includes laminating a dry photoresist layer to a substrate. The photoresist-laminated substrate is baked. An assembly is formed by laminating a plastic film to the baked, photoresist-laminated substrate. One or more electrically conductive interconnect layers are processed on a first surface of the laminated plastic film. The processing of the one or more electrically conductive interconnects includes photolithography. The assembly is baked and soaked in a liquid. The processed plastic film is then separated from the substrate.Type: ApplicationFiled: February 29, 2008Publication date: September 4, 2008Applicant: Raytheon CompanyInventor: Francis J. Morris
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Patent number: 7405869Abstract: Methods and apparatus for local oscillator generation are provided. In a method embodiment, a method of signal processing includes splitting a signal having a first frequency into at least a first portion and a second portion. The method also includes generating a second signal having a second frequency at a predetermined frequency difference from the first frequency by optically modulating the first portion. In addition, the method includes generating a third signal having a frequency component at a frequency that is approximately the same as the predetermined frequency difference from the first frequency by combining the second portion with the second signal.Type: GrantFiled: May 2, 2007Date of Patent: July 29, 2008Assignee: Raytheon CompanyInventors: Francis J. Morris, Premjeet Chahal
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Publication number: 20080099537Abstract: According to one embodiment of the invention, a method for sealing one or more vias comprises providing a first substrate having vias, forming an adhesion layer on an inner surface of the vias, sandwiching a solder layer between the first substrate and a second substrate, and elevating of the first substrate, second substrate, and solder layer to a temperature above a eutectic point and below a melting point of the solder layer. The act of elevating the solder layer to a temperature above the eutectic point and below the melting point causes the solder layer to flow into the vias in a generally consistent manner.Type: ApplicationFiled: October 31, 2006Publication date: May 1, 2008Applicant: Raytheon CompanyInventors: Premjeet Chahal, Billy D. Ables, Sankerlingam Rajendran, Francis J. Morris