Patents by Inventor Francis J. Pakulski

Francis J. Pakulski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Planarized thin film surface covered wire bonded semiconductor package
    Patent number: 5151559
    Abstract: This is a semiconductor chip in which the conductive path between the chip and the lead frame via wires can be easily and reproduceably improved. This is accomplished by improving the bond between the wires and the lead frame members to which the wires are joined and by creating additional contacts between each wire and its respective lead even if the bonded contact breaks or fails at or immediately adjacent to the bonding point. This is accomplished by placing an insulating layer on the active surface of each chip, carrying input and output bonding pads thereon, to which lead frame conductors have been connected by bonding wires.
    Type: Grant
    Filed: December 11, 1991
    Date of Patent: September 29, 1992
    Assignee: International Business Machines Corporation
    Inventors: H. Ward Conru, Gary H. Irish, Francis J. Pakulski, William J. Slattery, Stephen G. Starr, William C. Ward
  • Method of making a planarized thin film covered wire bonded semiconductor package
    Patent number: 5086018
    Abstract: A method of making a semiconductor chip in which the conductive path between the chip and the lead frame via wires can be easily and reproduceably improved. This is accomplished by improving the bond between the wires and the lead frame members to which the wires are joined and by creating additional contacts between each wire and its respective lead even if the bonded contact breaks or fails at or immediately adjacent to the bonding point. This is accomplished by placing an insulating layer on the active surface of each chip, carrying input and output bonding pads thereon, to which lead frame conductors have been connected by bonding wires.
    Type: Grant
    Filed: May 2, 1991
    Date of Patent: February 4, 1992
    Assignee: International Business Machines Corporation
    Inventors: H. Ward Conru, Gary H. Irish, Francis J. Pakulski, William J. Slattery, Stephen G. Starr, William C. Ward
  • Multi-port memory chip in a hierarchical memory
    Patent number: 4633440
    Abstract: A hierarchical memory system in which a lower level transfers data serially to an upper level and in parallel to a yet lower level. The lower level includes a two-port memory chip having a wide buffer for parallel accesses to the memory array, to the yet lower level, and to a serial buffer. The serial buffer is serially accessed to the upper level simultaneously with accesses to the wide buffer.
    Type: Grant
    Filed: December 31, 1984
    Date of Patent: December 30, 1986
    Assignee: International Business Machines
    Inventor: Francis J. Pakulski