Abstract: Technologies are described herein for activating one or more operating modes of a register in a meter. The register is operated in a first mode. Light detections indicating whether the register is exposed to light or isolated from light are read. It is determined whether a condition is met based on the light detections. Upon determining that the condition is met, operating the register in a second mode.

Abstract: Technologies are described herein for compensating for inaccuracies in flow measurement in real-time during accumulation of usage. A pulse count indicating an amount of flow in a meter over a measurement period is read. An average flow rate through the meter for the measurement period is determined and a correction factor is looked up from a table based on the average flow rate. A total usage accumulator for the meter is then updated with the amount of flow over the measurement period based on the pulse count and the correction factor.

Abstract: Technologies are described herein for activating one or more operating modes of a register in a meter. The register is operated in a first mode. Light detections indicating whether the register is exposed to light or isolated from light are read. It is determined whether a condition is met based on the light detections. Upon determining that the condition is met, operating the register in a second mode.

Abstract: Technologies are described herein for compensating for inaccuracies in flow measurement in real-time during accumulation of usage. A pulse count indicating an amount of flow in a meter over a measurement period is read. An average flow rate through the meter for the measurement period is determined and a correction factor is looked up from a table based on the average flow rate. A total usage accumulator for the meter is then updated with the amount of flow over the measurement period based on the pulse count and the correction factor.

Abstract: In lieu of merely forwarding different selected content including originally received decoder information (e.g., timing information) to a respective user for a newly selected data stream, a server modifies decoder information of a newly transmitted data stream in accordance with a previously transmitted stream (or a master clock associated with the user) such that respective decoder state information used to decode a first stream of content can also be used to decode a second stream of content. That is, the server encodes and transmits newly selected content to a requestor in accordance with current decoder state information already used by the requestor to decode previously received content. This enables splicing of content together from two or more asynchronous data streams into a single, contiguous data stream even though the data streams originate with different sets of timing information.

Abstract: A single data bus to a memory device can be split up into a number of data bus portions, each of which is managed by a different respective controller chip of multiple controller chips. During a memory access to a respective memory device, each of the multiple controller chips controls a different corresponding portion of the data bus to retrieve data from or store data to the memory device depending on whether the access is a read or write. To perform the data access, a synchronizer circuit (internal and/or external to the memory controller chips) synchronizes the multiple memory controller chips such that one of the memory controller chips drives the address bus and/or control signals to the memory device. After setting the address to the memory device, the memory controller chips either read data from or write data to the memory device based on the address.

Abstract: A system includes multiple input ports that forward received data (e.g., data packets) to each of multiple queues. Data received at the input ports of the system can be somewhat random or “bursty” at times. That is, the input ports can receive data at a variable bit rate or unspecified bit rate from an internal system source or an external source such as an FTP (File Transfer Protocol) server or SCSI disk array. The queues output data at a constant bit rate. A two-dimensional scheduler associated with the system forces random inbound server traffic from the input ports to adhere to a QoS (Quality of Service) agreement such that the random nature of the inbound traffic does not negatively affect the deterministic guarantees of existing server traffic output from the queues. In other words, techniques herein ensure adherence to QoS requirements among the data flows, without overflowing the queues.

Abstract: A single data bus to a memory device can be split up into a number of data bus portions, each of which is managed by a different respective controller chip of multiple controller chips. During a memory access to a respective memory device, each of the multiple controller chips controls a different corresponding portion of the data bus to retrieve data from or store data to the memory device depending on whether the access is a read or write. To perform the data access, a synchronizer circuit (internal and/or external to the memory controller chips) synchronizes the multiple memory controller chips such that one of the memory controller chips drives the address bus and/or control signals to the memory device. After setting the address to the memory device, the memory controller chips either read data from or write data to the memory device based on the address.

Abstract: An on-demand server system herein includes a memory controller that coordinates access to one or more flash-based memory devices. The flash devices store large amounts of video content that can be selectively viewed on-demand by each of multiple destinations over a respective network. In addition to having access to an array of flash memory devices, the memory controller has access to a corresponding read buffer and write buffer. Use of the read buffer and the write buffer enable the memory controller to switch between transferring data stored in the write buffer to the array of memory devices and transferring the data in the array of memory devices to the read buffer. The write buffer stores on-demand video content that can be selected for viewing by different users. The read buffer stores segments of the on-demand video content currently streamed to the users.

Abstract: A satellite receiver protection apparatus including a housing; an electrical power supply connector retained by the housing and adapted for connection to an AC outlet; a plurality of AC outlet sockets retained by the housing; and an electrical power surge suppressor retained within the housing and connected between the supply connector and the outlet sockets. Also included are an electrical input terminal retained by the housing and adapted for connection to a television antenna; an electrical output terminal retained by the housing and adapted for connection to a television receiver; and an electrical signal surge suppressor retained within the housing and connected between the input terminal and the output terminal.

Abstract: An emergency power supply including an input for connection to a power line, an output for connecting the input to electrical equipment so as to supply power thereto from the power line, a supplemental power supply connected to the output and adapted to supply power to the electrical equipment upon a power abnormality in the power line, an electrical energy storage means connected to the supplemental power supply and adapted to supply electrical energy thereto; and a circuit for detecting the abnormalities in the power line.

Abstract: A frequency lock system including an oscillator providing a switching output voltage that switches at a given frequency between fixed periods in each of first and second states and a reference source providing a variable reference voltage that periodically varies from and returns to a given voltage level at a predetermined frequency less than 1/2 the given frequency. A reference lock circuit provides a reference pulse of finite width in response to occurrence of the given voltage level and an oscillator lock circuit provides a control pulse of finite width a certain period after switching of the output from its first to its second state. In addition, a reset circuit resets the oscillator to initiate a new fixed period thereof at the second state in response to temporal coincidence of the reference and control pulses.

Abstract: A variable voltage power supply including a power source connected to an electrical energy storage means by an electronic switching means. Coupled to the energy storage means is a voltage output circuit providing an output voltage for a load and electrical energy transfer thereto from the energy storage means. A voltage comparator compares the output voltage with a periodically varying reference voltage providing output signals that switch the electronic switching means to cause the output voltage to track the reference voltage.

Abstract: A phase-lock system including an oscillator providing a switching output that continuously switches between first and second states, a trigger circuit for inducing switching of the oscillator, a sensing circuit monitoring the switching output and providing an anticipating indication of an imminent switching thereof from the first to the second state, and a primary voltage source providing a variable voltage that periodically varies from and returns to a given voltage level. Also included is a detector circuit monitoring the variable voltage and detecting the presence of the given voltage level and a synchronizing circuit responsive to the sensing and detector circuits and providing an input to the trigger circuit, the synchronizing circuit being operative to cause switching of the oscillator in response to the simultaneous provision of the anticipating indication by the sensing circuit and detection of the given level by the detector circuit.

Abstract: A circuit apparatus including a circuit interrupter connected between an AC supply and electrical equipment to be protected and operational in a first condition to transmit power therebetween and operational in a second condition to interrupt power transmission therebetween, a control circuit for producing the first condition in response to normal supply voltage and for producing said second condition in response to abnormal supply voltage, a delay circuit connected to the control circuit and adapted to produce a minimum time delay between successive occurrences of the first condition, an overvoltage circuit adapted to produce the second condition in response to a voltage from the supply that exceeds a predetermined maximum level, and an undervoltage circuit adapted to produce the second condition in response to a voltage from the supply that is below a given threshold level.

Abstract: The invention is an electronic isolation and surge suppression system including a housing defining cord and socket openings and retaining a surge suppressor connected to one end of an electrical cord, the other end of which terminates with a plug adapted for connection to an AC power source. Also retained by the housing are a plurality of multiple terminal electrical socket means and an electrical circuit connecting the sockets in a parallel combination that is in series with the suppressor. The electrical circuit includes an electrical filter connected between each of the socket means and the suppressor. Large voltage surges are eliminated by the suppressor, while the individual filters provide electrical isolation between electronic equipment connected to the individual sockets and isolation from AC power line noise and transients.

Abstract: A constant current circuit including a silicon controlled rectifier connected to transmit current flow from an ac supply to a load. A sensor circuit provides a load signal having a level dependent upon the current flow through the load and a reference circuit provides a reference signal having a predetermined given level. Receiving the load and reference signals is a comparator with an output connected to an SCR firing control network that furnishes firing signals to a gate of the silicon controlled rectifier. The output from the comparator varies the firing signal produced by a phase shift network in response to a reference signal level greater than the level of the load signal and retards the phase of the firing signal in response to a load signal level greater than the given reference level.

Abstract: An electrical system for use on aircraft and including a manually operated master switch for connecting a d.c. power supply to a supply bus that feeds electrical equipment on the aircraft. Energized by the supply bus is a monitor having a delayed output that activates an alarm indicating a closed condition of the master switch. The monitor is disabled by a sensing circuit that responds to the presence of electrical pulses generated on the bus by the aircraft's alternator. Upon a failure to open the master switch after the aircraft's engine has been stopped, the absence of alternator charging pulses on the bus prevents the sensor from de-activating the monitor which after a predetermined time delay energizes the alarm to warn the pilot of the condition that would result in discharging of the battery.

Abstract: An expanded scale measuring circuit including a four-arm bridge having a pair of input terminals for connections to a source of input voltage to be measured and a pair of measuring terminals between which are connected a current responsive meter. Located in one pair of the bridge arms are a resistor and diode that establish a reference voltage at one of the measuring terminals. The other pair of arms are formed by a voltage divider network including a zener diode that establishes a fixed reduction in the portion of input voltage applied to the other measuring terminal and therefore in the voltage appearing across the meter. By appropriately selecting resistance values for the divider network, a zero meter current condition is established for an input voltage at the bottom of a range of interest.