Abstract: This invention relates to a method of fabricating high resistive loads utilizing a single level polycide process in very large scale integrated circuits. By etching away a top silicide layer which exposes an underlying polysilicon layer and then implanting with a heavy dose of boron, a high resistive load on the integrated circuit is formed. Very often the highly resistive polysilicon load is implemented as a second polysilicon layer, which increases the process complexity vastly. This invention discloses the use of only one polycide layer to implement both the low resistive gate and interconnect and the high resistive polysilicon load needed to implement certain circuit functions.