Patents by Inventor Francis Koon Seong Poh

Francis Koon Seong Poh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High performance chip scale leadframe package with thermal dissipating structure and annular element and method of manufacturing package
    Patent number: 7323769
    Abstract: An integrated circuit package is disclosed. The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second face of the die pad is orthogonally offset from the second face of the leads so that the second face of the die pad and the second face of the leads are not coplanar. The package also comprises an integrated circuit chip substantially laterally disposed between the plurality of leads, and having a first face and a second face opposite to the first face. The first face of the integrated circuit chip is proximate to the second face of the die pad and the first face of the integrated circuit chip is coupled to the second face of the die pad. The package further comprises a plurality of wires that link the plurality of leads to the integrated circuit chip.
    Type: Grant
    Filed: May 8, 2006
    Date of Patent: January 29, 2008
    Assignee: United Test and Assembly Center Ltd.
    Inventors: Hien Boon Tan, Anthony Yi Sheng Sun, Francis Koon Seong Poh
  • High performance chip scale leadframe package and method of manufacturing the package
    Publication number: 20040124508
    Abstract: An integrated circuit package is disclosed. The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second face of the die pad is orthogonally offset from the second face of the leads so that the second face of the die pad and the second face of the leads are not coplanar. The package also comprises an integrated circuit chip substantially laterally disposed between the plurality of leads, and having a first face and a second face opposite to the first face. The first face of the integrated circuit chip is proximate to the second face of the die pad and the first face of the integrated circuit chip is coupled to the second face of the die pad. The package further comprises a plurality of wires that link the plurality of leads to the integrated circuit chip.
    Type: Application
    Filed: November 26, 2003
    Publication date: July 1, 2004
    Applicant: UNITED TEST AND ASSEMBLY TEST CENTER LTD.
    Inventors: Hien Boon Tan, Anthony Yi Sheng Sun, Francis Koon Seong Poh