Abstract: A digital device for detecting a metal object in the field of influence of a detector loop controlled by an oscillator which device creates a series of counting intervals and counts pulses during the intervals. The magnitude of the count during an interval is then indicative of metal detected by the loop. The count of a prior counting interval is stored and compared with the count of the next interval to determine whether or not there has been a detection. In this type of device there is provided an improvement wherein the magnitude of the counts stored during an interval is used to change the length of subsequent counting intervals. This maintains a generally high count magnitude for the counting interval to improve the sensitivity of the detecting device.

Abstract: An improvement in a digital device for detecting a metal object in the field of influence of an oscillator controlling loop, which digital device includes counter means for counting pulses during a counting interval, with the magnitude of the pulse count during the interval being indicative of the metal detected by the loop. The improvement includes means for creating a group of binary logic signals indicative of the difference between the pulse count and a selected reference count, these signals are allocated from a least significant to a more significant binary number, and reading means for reading the logic of at least some of the binary logic signals, which reading device includes means for indicating a detection when the signal being read has a selected binary logic pattern.

Abstract: An improvement in a digital coordinator of the type used for creating a background cycle defined by a series of control pulses repeatedly cycled between a first number, N.sub.1, and a second number, N.sub.2, with the time space between the N.sub.1 control pulse and the N.sub.2 control pulse being a background cycle length. This type of coordinator comprises a primary pulse counter means incremented by input counting pulses for creating one in a series of control pulses in response to a selected number of input counting pulses, wherein the input counting pulses have a selected frequency for determining the cycle speed of progression of the control pulses in successive count positions between the N.sub.1 control pulse and the N.sub.2 control pulse of a given background cycle, and shifting means for shifting the N.sub.1 control pulse with respect to time to correspond in time with a synchronization offset signal.

Abstract: There is provided a coordinator for creating a desired background cycle time and controlled logic conditions on selected output circuits during the background cycle which cycle and logic conditions are used in governing the signalization of a traffic intersection. This coordinator includes a pulse counter for counting between 0 and 99 upon receipt of counting pulses and having output means for creating a distinct signal upon counting to each digit in the range of 0 to 99. There is further provided means for controlling the frequency of the counting pulses to a frequency equal to one hundred divided by the time of a desired background cycle in seconds and decoding means for creating the selected logic conditions in output circuits when the counter counts to a selected number in the range of 0 to 99.