Patents by Inventor Francis Man-Chit Chow

Francis Man-Chit Chow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Mask set for fabricating integrated circuits and method of fabricating integrated circuits
    Patent number: 9401281
    Abstract: A mask set is described. In one implementation, the mask set includes: a first plurality of base layer masks, where each base layer mask of the first plurality of base layer masks includes a plurality of base layer tiles of a first tile size; a first plurality of top layer masks, where each top layer mask of the first plurality of top layer masks includes a plurality of first top layer tiles of the first tile size; and a second plurality of top layer masks, where each top layer mask of the second plurality of top layer masks includes a plurality of second top layer tiles of a second tile size; where the second tile size is different from the first tile size. Also, a method of fabricating a plurality of integrated circuits (ICs) is described.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: July 26, 2016
    Assignee: Altera Corporation
    Inventors: Jordan Plofsky, Chooi Pei Lim, Danny Biran, Francis Man-Chit Chow
  • Stacked die network-on-chip for FPGA
    Patent number: 8863065
    Abstract: A programmable device system includes one or more network-on-chip (NoC) die layers vertically connected to one or more programmable chip dice layers. The NoC die layer includes interconnects, a bus or non-blocking switches, and optionally memory blocks and direct memory access engines. The NoC die layer improves on-chip communications by providing fast and direct interconnection circuitry between various parts of the programmable chip die.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: October 14, 2014
    Assignee: Altera Corporation
    Inventors: Francis Man-Chit Chow, Rakesh H. Patel, Erhard Joachim Pistorius
  • Mask set for fabricating integrated circuits and method of fabricating integrated circuits
    Patent number: 8758961
    Abstract: A mask set is described. In one implementation, the mask set includes: a first layer mask including a plurality of first tiles of a first tile size; and a second layer mask including a plurality of second tiles of a second tile size, where the second tile size is different from the first tile size. Also, a method of fabricating a plurality of integrated circuits (ICs) is described. In one implementation, the method includes: using a first layer mask having a first tile size to fabricate a first layer of a first IC of the plurality of ICs and a first layer of a second IC of the plurality of ICs; and using a second layer mask having a second tile size to fabricate a second layer of the first IC, where the second tile size is different from the first tile size.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: June 24, 2014
    Assignee: Altera Corporation
    Inventors: Jordan Plofsky, Chooi Pei Lim, Danny Biran, Francis Man-Chit Chow
  • Stacked die network-on-chip for FPGA
    Patent number: 8719753
    Abstract: A programmable device system includes one or more network-on-chip (NoC) die layers vertically connected to one or more programmable chip dice layers. The NoC die layer includes interconnects, a bus or non-blocking switches, and optionally memory blocks and direct memory access engines. The NoC die layer improves on-chip communications by providing fast and direct interconnection circuitry between various parts of the programmable chip die.
    Type: Grant
    Filed: February 10, 2010
    Date of Patent: May 6, 2014
    Assignee: Altera Corporation
    Inventors: Francis Man-Chit Chow, Rakesh H. Patel, Erhard Joachim Pistorius
  • Stacked die network-on-chip for FPGA
    Patent number: 7701252
    Abstract: A programmable device system includes one or more network-on-chip (NoC) die layers vertically connected to one or more programmable chip dice layers. The NoC die layer includes interconnects, a bus or non-blocking switches, and optionally memory blocks and direct memory access engines. The NoC die layer improves on-chip communications by providing fast and direct interconnection circuitry between various parts of the programmable chip die.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: April 20, 2010
    Assignee: Altera Corporation
    Inventors: Francis Man-Chit Chow, Rakesh H. Patel, Erhard Joachim Pistorius