Patents by Inventor Francis P. O'Connell
Francis P. O'Connell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10241889Abstract: A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.Type: GrantFiled: March 8, 2017Date of Patent: March 26, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Heather L. Hanson, Venkat R. Indukuru, Francis P. O'Connell, Karthick Rajamani
-
Publication number: 20170177275Abstract: A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.Type: ApplicationFiled: March 8, 2017Publication date: June 22, 2017Inventors: HEATHER L. HANSON, VENKAT R. INDUKURU, FRANCIS P. O'CONNELL, KARTHICK RAJAMANI
-
Patent number: 9652356Abstract: A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.Type: GrantFiled: May 28, 2015Date of Patent: May 16, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Heather L. Hanson, Venkat R. Indukuru, Francis P. O'Connell, Karthick Rajamani
-
Patent number: 9645935Abstract: In an approach for sharing memory bandwidth in one or more processors, a processor receives a first set of monitored usage information for one or more processors executing one or more threads. A processor calculates impact of hardware data prefetching for each thread of the one or more threads, based on the first set of monitored usage information. A processor adjusts prefetch settings for the one or more threads, based on the calculated impact of hardware data prefetching for each thread of the one or more threads.Type: GrantFiled: January 13, 2015Date of Patent: May 9, 2017Assignee: International Business Machines CorporationInventors: Pradip Bose, Alper Buyuktosunoglu, Victor Javier Jimenez Perez, Francis P. O'Connell
-
Patent number: 9600392Abstract: A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.Type: GrantFiled: August 11, 2014Date of Patent: March 21, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Heather L. Hanson, Venkat R. Indukuru, Francis P. O'Connell, Karthick Rajamani
-
Publication number: 20160253264Abstract: In an approach for sharing memory bandwidth in one or more processors, a processor receives a first set of monitored usage information for one or more processors executing one or more threads. A processor calculates impact of hardware data prefetching for each thread of the one or more threads, based on the first set of monitored usage information. A processor adjusts prefetch settings for the one or more threads, based on the calculated impact of hardware data prefetching for each thread of the one or more threads.Type: ApplicationFiled: January 13, 2015Publication date: September 1, 2016Inventors: Pradip Bose, Alper Buyuktosunoglu, Victor Javier Jimenez Perez, Francis P. O'Connell
-
Publication number: 20160041594Abstract: A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.Type: ApplicationFiled: August 11, 2014Publication date: February 11, 2016Inventors: HEATHER L. HANSON, VENKAT R. INDUKURU, FRANCIS P. O'CONNELL, KARTHICK RAJAMANI
-
Publication number: 20160041775Abstract: A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.Type: ApplicationFiled: May 28, 2015Publication date: February 11, 2016Inventors: HEATHER L. HANSON, VENKAT R. INDUKURU, FRANCIS P. O'CONNELL, KARTHICK RAJAMANI
-
Patent number: 8949579Abstract: A processor of an information handling system (IHS) initiates an L3 cache prefetch operation in response to a demand load during instruction processing. The processor selects an L3 cache prefetch at random for tracking as a target prefetched instruction. The processor initiates an L1 cache target prefetch operation and stores the resultant target prefetched instruction in the L1 cache. If a demand load arrives, the processor analyzes the target prefetched instruction for effectiveness and determines the source of the prefetch data. If a demand does not arrive, the processor tests to determine if the particular prefetched instruction timed out in the cache and identifies the ineffectiveness of the prefetch operation. The processor samples multiple prefetch operations at random and generates a history of prefetch effectiveness and other useful prefetch information. The processor stores the prefetch effectiveness information to enable reduction or removal of ineffective prefetch operations.Type: GrantFiled: October 4, 2010Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Miles R. Dooley, Venkat R. Indukuru, Alex E. Mericas, Francis P. O'Connell
-
Patent number: 8909871Abstract: A data processing system includes a system memory and a cache hierarchy that caches contents of the system memory. According to one method of data processing, a storage modifying operation having a cacheable target real memory address is received. A determination is made whether or not the storage modifying operation has an associated bypass indication. In response to determining that the storage modifying operation has an associated bypass indication, the cache hierarchy is bypassed, and an update indicated by the storage modifying operation is performed in the system memory. In response to determining that the storage modifying operation does not have an associated bypass indication, the update indicated by the storage modifying operation is performed in the cache hierarchy.Type: GrantFiled: August 3, 2006Date of Patent: December 9, 2014Assignee: International Business Machines CorporationInventors: Ravi K. Arimilli, Francis P. O'Connell, Hazim Shafi, Derek E. Williams, Lixin Zhang
-
Patent number: 8856453Abstract: A prefetch unit includes a transience register and a length register. The transience register hosts an indication of transient for data stream prefetching. The length register hosts an indication of a stream length for data stream prefetching. The prefetch unit monitors the transience register and the length register. The prefetch unit generates prefetch requests of data streams with a transient property up to the stream length limit when the transience register indicates transient and the length register indicates the stream length limit for data stream prefetching. A cache controller coupled with the prefetch unit implements a cache replacement policy and cache coherence protocols. The cache controller writes data supplied from memory responsive to the prefetch requests into cache with an indication of transient. The cache controller victimizes cache lines with an indication of transient independent of the cache replacement policy.Type: GrantFiled: March 1, 2012Date of Patent: October 7, 2014Assignee: International Business Machines CorporationInventors: Jason N. Dale, Miles R. Dooley, Richard J. Eickemeyer, Bradly G. Frey, Yaoqing Gao, Francis P. O'Connell, Jeffrey A. Stuecheli
-
Publication number: 20130232320Abstract: A prefetch unit includes a transience register and a length register. The transience register hosts an indication of transient for data stream prefetching. The length register hosts an indication of a stream length for data stream prefetching. The prefetch unit monitors the transience register and the length register. The prefetch unit generates prefetch requests of data streams with a transient property up to the stream length limit when the transience register indicates transient and the length register indicates the stream length limit for data stream prefetching. A cache controller coupled with the prefetch unit implements a cache replacement policy and cache coherence protocols. The cache controller writes data supplied from memory responsive to the prefetch requests into cache with an indication of transient. The cache controller victimizes cache lines with an indication of transient independent of the cache replacement policy.Type: ApplicationFiled: March 1, 2012Publication date: September 5, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: JASON N. DALE, MILES R. DOOLEY, RICHARD J. EICKEMEYER, BRADLY G. FREY, YAOQING GAO, FRANCIS P. O'CONNELL, JEFFREY A. STUECHELI
-
Publication number: 20120084511Abstract: A processor of an information handling system (IHS) initiates an L3 cache prefetch operation in response to a demand load during instruction processing. The processor selects an L3 cache prefetch at random for tracking as a target prefetched instruction. The processor initiates an L1 cache target prefetch operation and stores the resultant target prefetched instruction in the L1 cache. If a demand load arrives, the processor analyses the target prefetched instruction for effectiveness and determines the source of the prefetch data. If a demand does not arrive, the processor tests to determine if the particular prefetched instruction timed out in the cache and identifies the infectiveness of the prefetch operation. The processor samples multiple prefetch operations at random and generates a history of prefetch effectiveness and other useful prefetch information. The processor stores the prefetch effectiveness information to enable reduction or removal of ineffective prefetch operations.Type: ApplicationFiled: October 4, 2010Publication date: April 5, 2012Applicant: International Business Machines CorporationInventors: Miles R. Dooley, Venkat R. Indukuru, Alex E. Mericas, Francis P. O'Connell
-
Publication number: 20080046736Abstract: A data processing system includes a system memory and a cache hierarchy that caches contents of the system memory. According to one method of data processing, a storage modifying operation having a cacheable target real memory address is received. A determination is made whether or not the storage modifying operation has an associated bypass indication. In response to determining that the storage modifying operation has an associated bypass indication, the cache hierarchy is bypassed, and an update indicated by the storage modifying operation is performed in the system memory. In response to determining that the storage modifying operation does not have an associated bypass indication, the update indicated by the storage modifying operation is performed in the cache hierarchy.Type: ApplicationFiled: August 3, 2006Publication date: February 21, 2008Inventors: Ravi K. Arimilli, Francis P. O'Connell, Hazim Shafi, Derek E. Williams, Lixin Zhang