Patents by Inventor Francis Xiaver Sicat De Rama

Francis Xiaver Sicat De Rama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems, devices and methods for automatically addressing serially connected slave devices
    Patent number: 11817969
    Abstract: A system for automatically addressing serially connected slave devices includes a master device and multiple slave devices each including a serial communication transceiver, an address input port, an address output port, and a controller. The system also includes a serial communication wiring bus connected between the serial communication transceivers of the master and slave devices, and at least one digital address line connected between the address input ports and the address output ports. Each controller is configured to receive a PWM or PFM signal from a previous one of the multiple slave devices, determine an address for the slave device including the controller according to the received PWM or PFM signal, and transmit a PWM or PFM signal indicative of the determined address to a subsequent one of the multiple slave devices.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: November 14, 2023
    Assignee: Astec International Limited
    Inventors: Vincent Vicente Vivar, James Larin David, Francis Xiaver Sicat De Rama
  • SYSTEMS, DEVICES AND METHODS FOR AUTOMATICALLY ADDRESSING SERIALLY CONNECTED SLAVE DEVICES
    Publication number: 20220263684
    Abstract: A system for automatically addressing serially connected slave devices includes a master device and multiple slave devices each including a serial communication transceiver, an address input port, an address output port, and a controller. The system also includes a serial communication wiring bus connected between the serial communication transceivers of the master and slave devices, and at least one digital address line connected between the address input ports and the address output ports. Each controller is configured to receive a PWM or PFM signal from a previous one of the multiple slave devices, determine an address for the slave device including the controller according to the received PWM or PFM signal, and transmit a PWM or PFM signal indicative of the determined address to a subsequent one of the multiple slave devices.
    Type: Application
    Filed: April 22, 2022
    Publication date: August 18, 2022
    Inventors: Vincent Vicente Vivar, James Larin David, Francis Xiaver Sicat De Rama