Abstract: The present invention is directed to a method and apparatus for simulating digital electronic systems. The signal integrity of a digital electronic system is assessed by analyzing traces (e.g. wires between components) for cross coupling. Problem areas are identified by monitoring storage components or output ports of the electronic system. Wires (traces), which carry signal transitions to the storage component or output ports are analyzed and quantified based on timing windows associated with the wires (traces). The clock transitions into a storage device are analyzed and vulnerability windows are identified for the storage device. The vulnerability windows are time periods when cross coupling may occur on a storage device. If a timing window overlaps a vulnerability window the timing window is considered a critical timing window. Devices driving the transition on wires with critical timing windows are then analyzed.

Abstract: A method of characterizing and simulating electronic systems for signal integrity is presented. Each device in the electronic system is associated with at least one vulnerability table and at least one vulnerability window. The vulnerability table is a three dimensional table that characterizes the operation of the device and includes line length on one axis, coupling efficiency on another axis and drivers size of a gate, on the third axis. In addition a number of vulnerability windows are presented. The vulnerability window is a time period when a storage device may store the wrong data because of signal integrity issues in the electronic system. A vulnerability window is developed for each input to a storage device in the system. In addition a vulnerability window is developed based on a number of failure mechanisms used to characterize the system. Lastly, a mapped vulnerability window is presented for devices such as logical gates, which provide input to the storage device.