Abstract: Systems of screening memory cells of a memory include modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven with respect to a nominal operating voltage on the wordline. In a write operation, one or both of the bitline and wordline may be overdriven or underdriven with respect to corresponding a nominal operating voltage. Such a system has margin control circuity, which may be in the form of bitline and wordline margin controls, to modulate bitline and wordline voltages, respectively, in the memory cells of the memory array.

Abstract: Systems of screening memory cells of a memory include modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven with respect to a nominal operating voltage on the wordline. In a write operation, one or both of the bitline and wordline may be overdriven or underdriven with respect to corresponding a nominal operating voltage. Such a system has margin control circuity, which may be in the form of bitline and wordline margin controls, to modulate bitline and wordline voltages, respectively, in the memory cells of the memory array.

Abstract: Systems and methods of screening memory cells by modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven as compared to a nominal operating voltage on the wordline. In a write operation, the one or both of the bitline and wordline may be overdriven or underdriven as compared to a nominal operating voltage of each. A built-in self test (BIST) system for screening a memory array has bitline and wordline margin controls to modulate bitline and wordline voltage, respectively, in the memory array.

Abstract: Systems and methods of screening memory cells by modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven as compared to a nominal operating voltage on the wordline. In a write operation, the one or both of the bitline and wordline may be overdriven or underdriven as compared to a nominal operating voltage of each. A built-in self test (BIST) system for screening a memory array has bitline and wordline margin controls to modulate bitline and wordline voltage, respectively, in the memory array.

Abstract: An adaptive voltage scaling technique includes using a temperature sensor arranged on a semiconductor die to determine a current die temperature of the semiconductor die, using a performance sensor arranged on a semiconductor die to determine a current performance metric of the semiconductor die, determining whether the current performance metric matches an expected performance metric based at least partially on the current die temperature and, if the current performance metric does not match the expected performance metric, indicate a performance sensor error, when a performance sensor error is indicated, determining an updated power supply voltage for correcting the performance sensor error, and causing a current power supply voltage supplied by a power supply voltage source of the semiconductor die to be changed to the updated power supply voltage.

Abstract: In an embodiment, a circuit configured for asymmetric ageing prevention in an integrated circuit (IC) comprises a primary clock configured to generate a primary clock signal, a secondary clock configured to generate a secondary clock signal, a state determination circuit, and a control circuit. The state determination circuit is configured to determine a current operating state associated with at least one of a primary clock condition and a power-on-reset condition in the IC. The control circuit is configured to generate a control signal in response to a determination of an first operating state. The control signal is configured to facilitate a transition from the primary clock to the secondary clock upon determination of the first operating state, and a transition from a safe operating mode to a normal operating mode upon determination of a second operating state. The secondary clock is associated with a safe operating mode of the IC.

Abstract: In an embodiment, a circuit configured for asymmetric ageing prevention in an integrated circuit (IC) comprises a primary clock configured to generate a primary clock signal, a secondary clock configured to generate a secondary clock signal, a state determination circuit, and a control circuit. The state determination circuit is configured to determine a current operating state associated with at least one of a primary clock condition and a power-on-reset condition in the IC. The control circuit is configured to generate a control signal in response to a determination of an first operating state. The control signal is configured to facilitate a transition from the primary clock to the secondary clock upon determination of the first operating state, and a transition from a safe operating mode to a normal operating mode upon determination of a second operating state. The secondary clock is associated with a safe operating mode of the IC.

Abstract: Power consumption is reduced by the use of a plurality of parameter reference targets, optimized for a subset of the complete temperature range. The prediction accuracy of the performance tracking sensor is optimized by using small segments of the operating temperature range.

Abstract: A method of adaptive voltage scaling is shown incorporating a lookup table holding manufacturing characterization data in conjunction with one or more precision analog temperature sensors used for correcting for temperature effects.

Abstract: A Bias Temperature Instability- (BTI-) resistance circuit is arranged to propagate a received clock signal through a clock tree. The state of the clock signal is inverted at a midpoint of the clock tree that is about the halfway point of the path of the propagated clock signal through the clock tree. The inversion of the clock signal at the midpoint mitigates BTI-aging effects of the BTI-resistant circuit when the clock signal is blocked by a clock gating signal, for example. The clock tree can be used to latch a data signal at an input latch of a logic block using the received clock signal, and to latch a data signal at an output latch of a logic block using a propagated clock signal that is output from the endpoint of the clock tree.