Patents by Inventor Francisco Cano

Francisco Cano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11831309
    Abstract: A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is coupled to the second current terminal at an intermediate node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: November 28, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Erkan Bilhan, Francisco A. Cano
  • Publication number: 20230238959
    Abstract: A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is connected to the second current terminal at an intermediate node and the fourth current terminal connected to a ground or supply node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.
    Type: Application
    Filed: April 5, 2023
    Publication date: July 27, 2023
    Inventors: Erkan Bilhan, Francisco A. Cano
  • Patent number: 11626875
    Abstract: A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is connected to the second current terminal at an intermediate node and the fourth current terminal connected to a ground or supply node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: April 11, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Erkan Bilhan, Francisco A. Cano
  • Publication number: 20190326909
    Abstract: A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is connected to the second current terminal at an intermediate node and the fourth current terminal connected to a ground or supply node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.
    Type: Application
    Filed: January 30, 2019
    Publication date: October 24, 2019
    Inventors: Erkan BILHAN, Francisco A. CANO
  • Publication number: 20190326910
    Abstract: A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is coupled to the second current terminal at an intermediate node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.
    Type: Application
    Filed: April 9, 2019
    Publication date: October 24, 2019
    Inventors: Erkan BILHAN, Francisco A. CANO
  • Publication number: 20120266123
    Abstract: Coherent analysis of asymmetric aging and statistical process variation. A method of designing a circuit includes preparing an initial netlist of components in the circuit. A plurality of components is selected from the initial netlist by a first statistical process. Further, a process variation netlist is prepared by replacing a plurality of initial operating parameters of the plurality of components with a plurality of process variation operating parameters. A plurality of high stress components is then identified in the process variation netlist and an aged netlist is prepared by replacing a set of operating parameters of the plurality of high stress components with a set of degraded operating parameters. The circuit is simulated using the aged netlist. The method also includes modifying the initial netlist according to a result of simulation and repeating the foregoing steps until a desired circuit performance is obtained.
    Type: Application
    Filed: April 12, 2011
    Publication date: October 18, 2012
    Applicant: Texas Instruments Incorporated
    Inventors: Palkesh JAIN, Vinod Menezes, Francisco Cano
  • Patent number: 8144533
    Abstract: A compensatory memory system is described. This memory system substantially improves performance by adapting an associated delay in a way that optimizes circuit performance.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: March 27, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Francisco A. Cano
  • Publication number: 20100265779
    Abstract: A compensatory memory system is described. This memory system substantially improves performance by adapting an associated delay in a way that optimizes circuit performance.
    Type: Application
    Filed: April 16, 2010
    Publication date: October 21, 2010
    Inventor: Francisco A. Cano
  • Patent number: 7446553
    Abstract: An apparatus and method to test components in a semiconductor test structure. On a semiconductor wafer, a test module implemented in one or more scribe lines between a plurality of semiconductor dies is used to test components in the semiconductor test structure. The test module may, for example, test electrical characteristics of chains of vias, transistors, and functional devices, such as oscillators. The test module contains a scan chain control coupled through a plurality of pass gates to each component to be tested. The scan chain control sequentially closes the pass gates to separately test the components in the semiconductor test structure. The test module further interfaces with an external testing device and the results of each test are compared with the expected results to identify faulty components.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: November 4, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Francisco Cano, Juan C. Martinez
  • Patent number: 7446552
    Abstract: An apparatus and method to test components in a semiconductor test structure. On a semiconductor wafer, a test module implemented in one or more scribe lines between a plurality of semiconductor dies is used to test components in the semiconductor test structure. The test module may, for example, test electrical characteristics of chains of vias, transistors, and functional devices, such as oscillators. The test module contains a scan chain control coupled through a plurality of pass gates to each component to be tested. The scan chain control sequentially closes the pass gates to separately test the components in the semiconductor test structure. The test module further interfaces with an external testing device and the results of each test are compared with the expected results to identify faulty components.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: November 4, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Francisco Cano, Juan C. Martinez
  • Patent number: 7382147
    Abstract: An apparatus and method to test components in a semiconductor test structure. On a semiconductor wafer, a test module implemented in one or more scribe lines between a plurality of semiconductor dies is used to test components in the semiconductor test structure. The test module may, for example, test electrical characteristics of chains of vias, transistors, and functional devices, such as oscillators. The test module contains a scan chain control coupled through a plurality of pass gates to each component to be tested. The scan chain control sequentially closes the pass gates to separately test the components in the semiconductor test structure. The test module further interfaces with an external testing device and the results of each test are compared with the expected results to identify faulty components.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: June 3, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Francisco Cano, Juan C. Martinez
  • Patent number: 7365556
    Abstract: An apparatus and method to test components in a semiconductor test structure. On a semiconductor wafer, a test module implemented in one or more scribe lines between a plurality of semiconductor dies is used to test components in the semiconductor test structure. The test module may, for example, test electrical characteristics of chains of vias, transistors, and functional devices, such as oscillators. The test module contains a scan chain control coupled through a plurality of pass gates to each component to be tested. The scan chain control sequentially closes the pass gates to separately test the components in the semiconductor test structure. The test module further interfaces with an external testing device and the results of each test are compared with the expected results to identify faulty components.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: April 29, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Francisco Cano, Juan C. Martinez
  • Publication number: 20070285104
    Abstract: An apparatus and method to test components in a semiconductor test structure. On a semiconductor wafer, a test module implemented in one or more scribe lines between a plurality of semiconductor dies is used to test components in the semiconductor test structure. The test module may, for example, test electrical characteristics of chains of vias, transistors, and functional devices, such as oscillators. The test module contains a scan chain control coupled through a plurality of pass gates to each component to be tested. The scan chain control sequentially closes the pass gates to separately test the components in the semiconductor test structure. The test module further interfaces with an external testing device and the results of each test are compared with the expected results to identify faulty components.
    Type: Application
    Filed: August 21, 2007
    Publication date: December 13, 2007
    Inventors: Francisco Cano, Juan Martinez
  • Publication number: 20070162808
    Abstract: An apparatus and method to test components in a semiconductor test structure. On a semiconductor wafer, a test module implemented in one or more scribe lines between a plurality of semiconductor dies is used to test components in the semiconductor test structure. The test module may, for example, test electrical characteristics of chains of vias, transistors, and functional devices, such as oscillators. The test module contains a scan chain control coupled through a plurality of pass gates to each component to be tested. The scan chain control sequentially closes the pass gates to separately test the components in the semiconductor test structure. The test module further interfaces with an external testing device and the results of each test are compared with the expected results to identify faulty components.
    Type: Application
    Filed: March 9, 2007
    Publication date: July 12, 2007
    Inventors: Francisco Cano, Juan Martinez
  • Publication number: 20070145999
    Abstract: An apparatus and method to test components in a semiconductor test structure. On a semiconductor wafer, a test module implemented in one or more scribe lines between a plurality of semiconductor dies is used to test components in the semiconductor test structure. The test module may, for example, test electrical characteristics of chains of vias, transistors, and functional devices, such as oscillators. The test module contains a scan chain control coupled through a plurality of pass gates to each component to be tested. The scan chain control sequentially closes the pass gates to separately test the components in the semiconductor test structure. The test module further interfaces with an external testing device and the results of each test are compared with the expected results to identify faulty components.
    Type: Application
    Filed: March 9, 2007
    Publication date: June 28, 2007
    Inventors: Francisco Cano, Juan Martinez
  • Publication number: 20060044001
    Abstract: An apparatus and method to test components in a semiconductor test structure. On a semiconductor wafer, a test module implemented in one or more scribe lines between a plurality of semiconductor dies is used to test components in the semiconductor test structure. The test module may, for example, test electrical characteristics of chains of vias, transistors, and functional devices, such as oscillators. The test module contains a scan chain control coupled through a plurality of pass gates to each component to be tested. The scan chain control sequentially closes the pass gates to separately test the components in the semiconductor test structure. The test module further interfaces with an external testing device and the results of each test are compared with the expected results to identify faulty components.
    Type: Application
    Filed: September 2, 2005
    Publication date: March 2, 2006
    Inventors: Francisco Cano, Juan Martinez
  • Patent number: 6581201
    Abstract: An integrated circuit 210 has a power grid formed from a first set of power buses 201a and 202a on a metal interconnect level M1, a second set of power buses 203a and 204a on interconnect level M4, and a third set of power buses 205a and 206a on interconnect level M5. The set of power buses on level M4 are oriented in the same direction as the set of power buses on level M1, and both sets of buses are located coincidentally. A high power logic cell 220 is pre-defined with a set of M1-M4 power vias 221 and 222 so that logic cell 220 can be positioned in a horizontal row unconstrained by pre-positioned M1-M4 power vias. Dummy cell 230 with M1-M4 power vias is positioned as needed so as not to exceed a maximum strapping distance D1. A maximum value for distance D1 is selected based on dynamic power requirements of nearby logic cells 250a-n as determined by simulation. A method for designing and fabricating integrated circuit 210 is described.
    Type: Grant
    Filed: October 2, 2001
    Date of Patent: June 17, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Francisco A. Cano, David A. Thomas, Clive Bittlestone
  • Patent number: 6381704
    Abstract: A clock generation circuit 122 with a selectable non-overlap time period is described for use on an integrated circuit. A master clock signal M which has a latching edge is formed in response to a reference clock signal fclk. A slave clock signal S which has a driving edge is also formed in response to the reference clock signal. The driving edge of slave clock S is delayed by a non-overlap feedback path 504 so that the driving edge is delayed by the non-overlap time period after the latching edge of master clock M. The value of the non-overlap time period is selected by switching delay circuitry 531 in or out of the non-overlap feedback path on signal line 504. A control signal STRSTST is set high or low to select the value of the non-overlap time period. A sense circuit 561 or a scan latch 562 also can select the non-overlap time period.
    Type: Grant
    Filed: January 29, 1999
    Date of Patent: April 30, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Francisco A. Cano, Rajib Nag, Robert E. Farrell
  • Patent number: 6363516
    Abstract: In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures. A method is provided for extracting parasitic data in a hierarchical manner from a trial layout of the integrated circuit. Intracellular parasitic data representative each cell type used in the integrated circuit is extracted only once, regardless of the number of times the cell is instantiated in the integrated circuit. For each instance of each cell, a portion of intercell signal lines that are routed over that instance of the cell are cut out in cookie cutter fashion by specifying an area in the trial layout corresponding to the instance of the cell such that the portion of intercell signal lines within the area can be processed apart from the remaining portion of the intercell signal lines.
    Type: Grant
    Filed: November 12, 1999
    Date of Patent: March 26, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Francisco A. Cano, Nagaraj N. Savithri, Vijaya Gunturi
  • Publication number: 20020013931
    Abstract: An integrated circuit 210 has a power grid formed from a first set of power buses 201a and 202a on a metal interconnect level M1, a second set of power buses 203a and 204a on interconnect level M4, and a third set of power buses 205a and 206a on inter-connect level M5. The set of power buses on level M4 are oriented in the same direction as the set of power buses on level M1, and both sets of buses are located coincidentally. A high power logic cell 220 is pre-defined with a set of M1-M4 power vias 221 and 222 so that logic cell 220 can be positioned in a horizontal row unconstrained by pre-positioned M1-M4 power vias. Dummy cell 230 with M1-M4 power vias is positioned as needed so as not to exceed a maximum strapping distance D1. A maximum value for distance D1 is selected based on dynamic power requirements of nearby logic cells 250a-n as determined by simulation. A method for designing and fabricating integrated circuit 210 is described.
    Type: Application
    Filed: October 2, 2001
    Publication date: January 31, 2002
    Inventors: Francisco A. Cano, David A. Thomas, Clive Bittlestone