Patents by Inventor FRANCISCO CHAIDEZ

FRANCISCO CHAIDEZ has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Electronic devices with embedded die interconnect structures, and methods of manufacture thereof
    Patent number: 9401338
    Abstract: An embodiment of an electronic device includes an IC die with a top surface and a bond pad exposed at the top surface. A stud bump (or stack of stud bumps) is connected to the bond pad, and the stud bump and die are encapsulated with encapsulant. A trench is formed from a top surface of the encapsulant to the stud bump, resulting in the formation of a trench-oriented surface of the stud bump, which is exposed at the bottom of the trench. An end of an interconnect is connected to the trench-oriented surface of the stud bump. The interconnect extends above the encapsulant top surface, and may be coupled to another IC die of the same electronic device, another IC die that is distinct from the device, or another conductive feature of the device or a larger electronic system in which the device is incorporated.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: July 26, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Alan J. Magnus, Francisco Chaidez
  • ELECTRONIC DEVICES WITH EMBEDDED DIE INTERCONNECT STRUCTURES, AND METHODS OF MANUFACTURE THEREOF
    Publication number: 20140145325
    Abstract: An embodiment of an electronic device includes an IC die with a top surface and a bond pad exposed at the top surface. A stud bump (or stack of stud bumps) is connected to the bond pad, and the stud bump and die are encapsulated with encapsulant. A trench is formed from a top surface of the encapsulant to the stud bump, resulting in the formation of a trench-oriented surface of the stud bump, which is exposed at the bottom of the trench. An end of an interconnect is connected to the trench-oriented surface of the stud bump. The interconnect extends above the encapsulant top surface, and may be coupled to another IC die of the same electronic device, another IC die that is distinct from the device, or another conductive feature of the device or a larger electronic system in which the device is incorporated.
    Type: Application
    Filed: November 29, 2012
    Publication date: May 29, 2014
    Inventors: ALAN J. MAGNUS, FRANCISCO CHAIDEZ