Abstract: A device for a gateway controller for frame normalization comprises processing circuitry that is configured to receive one or more ingress frames of bits, wherein each ingress frame has one of multiple frame formats included in a set of frame formats, and is configured to convert each ingress frame into a normalized frame of bits, wherein each normalized frame has a normalized frame format.

Abstract: A program flow monitoring (PFM) device for a gateway (GW) device is provided. The PFM device comprises a configurable functional state machine (FSM) configured to model a behavior of a monitored processing stage of the GW device. The PFM device is configured to predict an expected behavior of the monitored processing stage in dependence of an input of the monitored processing stage and the behavioral model; compare the expected behavior with an actual behavior of the monitored processing stage based on an output of the monitored processing stage; and selectively generate a fault notification in dependence of a result of the comparison.

Abstract: A communication network comprises a central processing unit, data ingress ports and data egress ports configured to exchange data with a further network device of the communication network, and a plurality of co-processors that comprises frame normalization co-processors, ingress queuing co-processors, filtering and policing co-processors, intermediate queuing co-processors, a gatewaying co-processor, egress queuing co-processors, and a traffic shaping co-processor. The central processing unit configures and controls the data ingress ports, the data egress ports, and the plurality of co-processors to implement data processing paths in parallel or in a pipeline between the ingress ports and the egress ports.

Abstract: A microchip includes a central processing unit (CPU) configured to execute a software application. The microchip further includes an Ethernet interface configured to transmit Ethernet packets to and receive Ethernet packets from an external debugging entity. The microchip further includes an on-chip debug and trace module configured to transform debugging data and trace data from the CPU into a stream of Ethernet packets, and to provide the stream of Ethernet packets to the Ethernet interface for transmitting the stream of Ethernet packets to the external debugging entity.

Abstract: A controller is configured to: obtain a state of each of a plurality of queues of a network node; determine, based on the states of the queues, whether the utilization of one or more queues exceeds one or more thresholds; generate one or more new entries for a gate control list of the network node that controls the plurality of queues, if one or more thresholds are exceeded; and provide the one or more new entries to the network node. Further, a network node is configured to provide a state of each of a plurality of queues to a controller, and obtain one or more new entries for a gate control list of the network node that controls the plurality of queues, from the controller.

Abstract: The present disclosure relates to controlling queue release in a network. In particular, the disclosure proposes a controller configured to obtain a state of each of a plurality of queues of a network node and determine, based on the states of the queues, whether the utilization of one or more queues exceeds one or more thresholds. If one or more thresholds are exceeded, the controller is configured to generate one or more new priority entries for one or more queues of the plurality of queues and provide the one or more new priority entries to the one or more queues of the network node. Further, the disclosure proposes a network node being configured to provide a state of each of a plurality of queues to a controller, and obtain one or more new priority entries for one or more queues of the plurality of queues from the controller.

Abstract: An electronic control unit (ECU) for vehicles is described, including memory to store encrypted data and unencrypted data; a main control unit operatively connected to memory to access unencrypted data; and a hardware encryption-decryption device operatively connected to memory to access encrypted/decrypted data for decryption using a hardware algorithm and for encryption using a hardware algorithm. Data in the memory is decrypted by the hardware encryption-decryption device using the hardware algorithm and stored in memory for use by the main control unit. Data in memory is encrypted by the hardware encryption-decryption device using the hardware algorithm for storage in memory. The main control unit and the hardware encryption-decryption device are separate integrate circuits on a same substrate or and are connected by a bus and can process data in parallel. An external bus can communicate encrypted information with the ECU to allow encrypt/decrypt at run time (on-the-fly) and wire-speed.

Abstract: An electronic control unit (ECU) for vehicles is described, including memory to store encrypted data and unencrypted data; a main control unit operatively connected to memory to access unencrypted data; and a hardware encryption-decryption device operatively connected to memory to access encrypted/decrypted data for decryption using a hardware algorithm and for encryption using a hardware algorithm. Data in the memory is decrypted by the hardware encryption-decryption device using the hardware algorithm and stored in memory for use by the main control unit. Data in memory is encrypted by the hardware encryption-decryption device using the hardware algorithm for storage in memory. The main control unit and the hardware encryption-decryption device are separate integrate circuits on a same substrate or and are connected by a bus and can process data in parallel. An external bus can communicate encrypted information with the ECU to allow encrypt/decrypt at run time (on-the-fly) and wire-speed.

Abstract: An electronic control unit (ECU) for vehicles is described, including memory to store encrypted data and unencrypted data; a main control unit operatively connected to memory to access unencrypted data; and a hardware encryption-decryption device operatively connected to memory to access encrypted/decrypted data for decryption using a hardware algorithm and for encryption using a hardware algorithm. Data in the memory is decrypted by the hardware encryption-decryption device using the hardware algorithm and stored in memory for use by the main control unit. Data in memory is encrypted by the hardware encryption-decryption device using the hardware algorithm for storage in memory. The main control unit and the hardware encryption-decryption device are separate integrate circuits on a same substrate or SOC and are connected by a bus and can process data in parallel. An external bus can communicate encrypted information with the ECU to allow encrypt/decrypt at run time (on-the-fly) and wire-speed.

Abstract: An electronic control unit (ECU) for vehicles is described, including memory to store encrypted data and unencrypted data; a main control unit operatively connected to memory to access unencrypted data; and a hardware encryption-decryption device operatively connected to memory to access encrypted/decrypted data for decryption using a hardware algorithm and for encryption using a hardware algorithm. Data in the memory is decrypted by the hardware encryption-decryption device using the hardware algorithm and stored in memory for use by the main control unit. Data in memory is encrypted by the hardware encryption-decryption device using the hardware algorithm for storage in memory. The main control unit and the hardware encryption-decryption device are separate integrate circuits on a same substrate or SOC and are connected by a bus and can process data in parallel. An external bus can communicate encrypted information with the ECU to allow encrypt/decrypt at run time (on-the-fly) and wire-speed.