Patents by Inventor Francisco Gilabert Villamon

Francisco Gilabert Villamon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8085659
    Abstract: The invention falls within the technology of multistage interconnection network such as fat-trees, comprising at least one switch located at a stage (s) and configured to send, through an output port from a number (k) of output ports forming an ordered list, at least a data packet containing a destination address identified by a n-tuple with a plurality (n) of components (pn?1, . . . , p1, p0), and s?{0 . . . (n?1)}. The invention has application for both source and distributed routing, as deterministic and as adaptive routing, selecting an output port to be the unique or the default option to forward the packets at the switch which is the output port that has a position in the ordered list of output ports corresponding to the component (ps) of the destination address at the position given by the stage (s) of the switch.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: December 27, 2011
    Assignee: Universidad Politecnica de Valencia
    Inventors: Jose Francisco Duato Marin, Francisco Gilabert Villamon, Crispin Gomez Requena, Maria Engracia Gomez Requena, Pedro Juan Lopez Rodriguez
  • Publication number: 20090059913
    Abstract: The invention falls within the technology of multistage interconnection network such as fat-trees, comprising at least one switch located at a stage (s) and configured to send, through an output port from a number (k) of output ports forming an ordered list, at least a data packet containing a destination address identified by a n-tuple with a plurality (n) of components (pn?1, . . . , p1, p0), and s?{0 . . . (n?1)}. The invention has application for both source and distributed routing, as deterministic and as adaptive routing, selecting an output port to be the unique or the default option to forward the packets at the switch which is the output port that has a position in the ordered list of output ports corresponding to the component (ps) of the destination address at the position given by the stage (s) of the switch.
    Type: Application
    Filed: August 28, 2007
    Publication date: March 5, 2009
    Applicant: UNIVERSIDAD POLITECNICA DE VALENCIA
    Inventors: Jose Francisco Duato Marin, Francisco Gilabert Villamon, Crispin Gomez Requena, Maria Engracia Gomez Requena, Pedro Juan Lopez Rodriguez