Patents by Inventor Francisco-Javier Veredas-Ramirez

Francisco-Javier Veredas-Ramirez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080079460
    Abstract: A mask programmable logic cell for configuration of at least one either LUT-based and MUX-based configurable cell comprises a first set of 2:1 multiplexers each having two input terminals and one select terminal and a second set of 4:1 multiplexers each having four input terminals and comprising three hierarchal arranged 2:1 multiplexers. A LUT-based configurable cell, a MUX-based configurable cell arrangement and a configurable logic array is provided. Furthermore, a mask programmable basic cell and a mask programmable gate array is provided.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 3, 2008
    Applicant: Infineon Technologies AG
    Inventors: Francisco-Javier Veredas-Ramirez, Siegmar Koeppe
  • Patent number: 7323904
    Abstract: A read out device for reading out a data word from a memory cell is described. The read out device has memory cells, inputs for input variables for selecting a memory cell and a hierarchical arrangement of multiplexers having N hierarchical levels. The control inputs of the multiplexers of a hierarchical level are connected to an input, the inputs of the hierarchical arrangement of multiplexers are connected to the outputs of the memory cells and the number of memory cells is less than 2N.
    Type: Grant
    Filed: February 4, 2005
    Date of Patent: January 29, 2008
    Assignee: Infineon Technologies AG
    Inventors: Francisco-Javier Veredas-Ramirez, Michael Scheppler
  • Publication number: 20050174144
    Abstract: A read out device for reading out a data word from a memory cell is described. The read out device has memory cells, inputs for input variables for selecting a memory cell and a hierarchical arrangement of multiplexers having N hierarchical levels. The control inputs of the multiplexers of a hierarchical level are connected to an input, the inputs of the hierarchical arrangement of multiplexers are connected to the outputs of the memory cells and the number of memory cells is less than 2N.
    Type: Application
    Filed: February 4, 2005
    Publication date: August 11, 2005
    Inventors: Francisco-Javier Veredas-Ramirez, Michael Scheppler