Patents by Inventor Francisco L. Duran
Francisco L. Duran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230384947Abstract: Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of the physical memory address mapping does not require a processing system to be rebooted and has various applications in connection with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.Type: ApplicationFiled: June 12, 2023Publication date: November 30, 2023Inventors: Joseph L. Greathouse, Alan D. Smith, Francisco L. Duran, Felix Kuehling, Anthony Asaro
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Patent number: 11687251Abstract: Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of the physical memory address mapping does not require a processing system to be rebooted and has various applications in connection with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.Type: GrantFiled: September 28, 2021Date of Patent: June 27, 2023Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Joseph L. Greathouse, Alan D. Smith, Francisco L. Duran, Felix Kuehling, Anthony Asaro
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Publication number: 20230097344Abstract: Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of the physical memory address mapping does not require a processing system to be rebooted and has various applications in connection with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.Type: ApplicationFiled: September 28, 2021Publication date: March 30, 2023Inventors: Joseph L. Greathouse, Alan D. Smith, Francisco L. Duran, Felix Kuehling, Anthony Asaro
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Patent number: 10866895Abstract: A method of managing memory access includes receiving, at an input output memory management unit, a memory access request from a device. The memory access request includes a virtual steering tag associate associated with a virtual machine. The method further includes translating the virtual steering tag to a physical steering tag directing memory access of a cache memory associated with a processor core of a plurality of processor cores. The virtual machine is implemented on the processor core. The method also includes accessing the cache memory to implement the memory access request.Type: GrantFiled: December 18, 2018Date of Patent: December 15, 2020Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Philip Ng, Nippon Harshadk Raval, Francisco L. Duran
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Publication number: 20200192802Abstract: A method of managing memory access includes receiving, at an input output memory management unit, a memory access request from a device. The memory access request includes a virtual steering tag associate associated with a virtual machine. The method further includes translating the virtual steering tag to a physical steering tag directing memory access of a cache memory associated with a processor core of a plurality of processor cores. The virtual machine is implemented on the processor core. The method also includes accessing the cache memory to implement the memory access request.Type: ApplicationFiled: December 18, 2018Publication date: June 18, 2020Inventors: Philip NG, Nippon Harshadk RAVAL, Francisco L. DURAN
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Patent number: 9423847Abstract: A processor includes a processor core and a power management controller operable to receive a timer event, store the timer event, generate a hardware system sleep command to enter a hardware system sleep state, and restore the timer event upon exiting from the hardware system sleep state.Type: GrantFiled: December 20, 2011Date of Patent: August 23, 2016Assignee: Advanced Micro Devices, Inc.Inventors: Alexander J. Branover, Krishna S Bernucho, Maurice B Steinman, Ming L. So, Mom-Eng Ng, Xiaogang Zheng, Paul Blinzer, Francisco L Duran, Walter G. Fry, Ali Ibrahim, Andrew W. Lueck, Dan P Shimizu, Gary H. Simpson, Laura M. Smith
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Publication number: 20140157026Abstract: Methods and apparatus for dynamically adjusting a power level of an electronic device (100) are disclosed. In an embodiment, an electronic device (100) receives a usage pattern of the electronic device (100) (e.g., typically used 9:00 AM to 5:00 PM on weekdays). The electronic device (100) then dynamically adjusts a wake up timer (204) associated with the electronic device (100) based on the usage pattern (e.g., expire at 8:50 am the next morning, which is 10 minutes before usage typically resumes for that day). In response to an expiration of the dynamically adjusted wake up timer (204), the electronic device (100) increases the power level of the electronic device (100) (e.g., transition from hibernate mode to standby mode, possibly via other intervening power modes, for faster startup in anticipation of resumed usage).Type: ApplicationFiled: December 5, 2012Publication date: June 5, 2014Applicants: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Ming L. So, Xiaogang Zheng, ChangHwa Lee, Francisco L. Duran, Wayne Louie, Stephen H. Cheng
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Publication number: 20130159750Abstract: A processor includes a processor core and a power management controller operable to receive a timer event, store the timer event, generate a hardware system sleep command to enter a hardware system sleep state, and restore the timer event upon exiting from the hardware system sleep state.Type: ApplicationFiled: December 20, 2011Publication date: June 20, 2013Inventors: Alexander J. Branover, Krishna S. Bernucho, Maurice B. Steinman, Ming L. So, Mom-Eng Ng, Xiaogang Zheng, Paul Blinzer, Francisco L. Duran, Walter G. Fry, Ali Ibrahim, Andrew W. Lueck, Dan P. Shimizu, Gary H. Simpson, Laura M. Smith
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Patent number: 7747881Abstract: A system and method for managing performance states of a processor. An enclosure comprises a first processing board with a processor and a second processing board with a processor. A service processor may also be coupled to the enclosure via an interconnect. The second processing board is configured to store a value indicative of a maximum processor performance state for a processor on the second board. In response to a detected request for a transition to a first processor performance state, the processor on the second board is configured to transition to the first processor performance state, if the first processor state is less than or equal to the maximum processor performance state; and transition to the maximum processor performance state, if the first processor state is greater than the maximum processor state. The second processor board may store the value in response to a an operating environment condition detected elsewhere within the enclosure.Type: GrantFiled: August 14, 2006Date of Patent: June 29, 2010Assignee: GLOBALFOUNDRIES Inc.Inventors: Francisco L. Duran, W. Paul Montgomery, David F. Tobias
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Publication number: 20080040622Abstract: A system and method for managing performance states of a processor. An enclosure comprises a first processing board with a processor and a second processing board with a processor. A service processor may also be coupled to the enclosure via an interconnect. The second processing board is configured to store a value indicative of a maximum processor performance state for a processor on the second board. In response to a detected request for a transition to a first processor performance state, the processor on the second board is configured to transition to the first processor performance state, if the first processor state is less than or equal to the maximum processor performance state; and transition to the maximum processor performance state, if the first processor state is greater than the maximum processor state. The second processor board may store the value in response to a an operating environment condition detected elsewhere within the enclosure.Type: ApplicationFiled: August 14, 2006Publication date: February 14, 2008Inventors: Francisco L. Duran, W. Paul Montgomery, David F. Tobias
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Patent number: 7035954Abstract: A technique for rebalancing performance levels of one or more add-in cards is presented. Rebalancing occurs whenever a hot-plug event occurs and a change in status of a mismatch condition occurs. For example, if an add-in card is inserted that is unable to operate at the current performance level, rebalancing of the performance level occurs. Thus, for an insertion event, the performance level of all cards may be lowered. Alternatively, if an add-in card is removed and a mismatch is resolved, rebalancing of the performance level occurs. Thus, for a removal event, the performance level may be increased. The rebalancing includes disabling any enabled cards and enabling all cards at a different performance level. In one embodiment, the cards are sorted according to highest performance level available and enabled in an order of lowest to highest of the highest performance level available.Type: GrantFiled: April 3, 2003Date of Patent: April 25, 2006Assignee: Advanced Micro Devices, Inc.Inventor: Francisco L. Duran
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Patent number: 6084573Abstract: An analog joystick interface system for overcoming the deficiencies of the conventional analog joystick interface by supporting positional tracking in both a legacy and an enhanced mode. In the legacy mode, the host calculates the relative physical orientation of a positional grip of an analog joystick by relying upon continuous polling techniques. In the enhanced mode, a watch dog timer relieves the host of the need to continuously poll by directly providing the host with positional data concerning the relative physical orientation of the positional grip. The ability of the joystick interface to provide both the legacy and enhanced modes ensures that compability issues concerning the legacy DOS-based software applications and CPU allocation problems associated with continuous polling are resolved without considerably increasing cost or complexity of the joystick interface.Type: GrantFiled: March 12, 1998Date of Patent: July 4, 2000Assignee: S3 IncorporatedInventors: Winston Tsai, Francisco L. Duran, Seng-Khoon Tng