Abstract: A transceiver for sending and receiving data from a controller area network (CAN) bus is disclosed. The transceiver includes a microcontroller port, a transmitter and a receiver, wherein the transceiver is configured to determine bit timings from a data frame received by the receiver. The transceiver is further configured to detect attempts to introduce a signal glitch in a predetermined portion of the data frame and upon detection of the signal glitch, the transceiver is configured to invalidate the data frame on a transmission line and/or disable the transmitter for a predetermined period.

Abstract: A transceiver for sending and receiving data from a controller area network (CAN) bus is disclosed. The transceiver includes a microcontroller port, a transmitter and a receiver. The transceiver is configured to receive a data frame from a microcontroller via the microcontroller port and to determine if the microcontroller is authorized to send the data frame or part of it based on a message identifier in the data frame and the outcome of the arbitration process. If the microcontroller is unauthorized to send the data, the transceiver is configured to invalidate the data frame and disconnect the microcontroller from the CAN bus for a predetermined period.

Abstract: A transceiver for sending and receiving data from a controller area network (CAN) bus is disclosed. The transceiver includes a microcontroller port, a transmitter and a receiver. The transceiver is configured to detect a CRC delimiter or an error signal in a CAN frame and after the detection, allow a microcontroller coupled with the microcontroller port to only send a predetermined data pattern until a bus idle is detected.

Abstract: A transceiver for sending and receiving data from a controller area network (CAN) bus is disclosed. The transceiver includes a microcontroller port, a transmitter and a receiver, wherein the transceiver is configured to determine bit timings from a data frame received by the receiver. The transceiver is further configured to detect attempts to introduce a signal glitch in a predetermined portion of the data frame and upon detection of the signal glitch, the transceiver is configured to invalidate the data frame on a transmission line and/or disable the transmitter for a predetermined period.

Abstract: A transceiver for sending and receiving data from a controller area network (CAN) bus is disclosed. The transceiver includes a microcontroller port, a transmitter and a receiver. The transceiver is configured to receive a data frame from a microcontroller via the microcontroller port and to determine if the microcontroller is authorized to send the data frame or part of it based on a message identifier in the data frame and the outcome of the arbitration process. If the microcontroller is unauthorized to send the data, the transceiver is configured to invalidate the data frame and disconnect the microcontroller from the CAN bus for a predetermined period.

Abstract: As may be implemented in accordance with one or more embodiments, an event manager provides control of a battery-powered internal power supply. The power supply has a control port that receives a control signal for activating and deactivating the internal power supply, and one or more output ports for providing a power signal. The event manager includes a plurality of system-event circuits that detect activity signals corresponding to a respective one of a plurality of system events. An event validation circuit, which is powered by the power signal, provides a validation signal that is based upon an activity signal detected by the event manager circuit and that indicates that the internal power supply should provide the power signal in a non-sleep power-operation mode.

Abstract: As may be implemented in accordance with one or more embodiments, an event manager provides control of a battery-powered internal power supply. The power supply has a control port that receives a control signal for activating and deactivating the internal power supply, and one or more output ports for providing a power signal. The event manager includes a plurality of system-event circuits that detect activity signals corresponding to a respective one of a plurality of system events. An event validation circuit, which is powered by the power signal, provides a validation signal that is based upon an activity signal detected by the event manager circuit and that indicates that the internal power supply should provide the power signal in a non-sleep power-operation mode.

Abstract: Various exemplary aspects are directed to apparatuses and methods involving switches communicatively-coupled on a bus where one or more of the switches operate to block signals from passing through the switch in a first mode, and to pass signals through the switch in a second mode. A logic circuit is responsive to addressing information received in the first mode, by storing and configuring the apparatus with the address information. The logic circuit ignores address information received in the second mode (e.g., does not reconfigure the apparatus with address information received in the second mode).

Abstract: Various exemplary aspects are directed to apparatuses and methods involving switches communicatively-coupled on a bus where one or more of the switches operate to block signals from passing through the switch in a first mode, and to pass signals through the switch in a second mode. A logic circuit is responsive to addressing information received in the first mode, by storing and configuring the apparatus with the address information. The logic circuit ignores address information received in the second mode (e.g., does not reconfigure the apparatus with address information received in the second mode).

Abstract: A data processing apparatus receives a communication signal that contains temporally successive bits. A programmable processor circuit executes a plurality of series of programmed instructions for operations such as parity checking, each at a time of reception of a respective one of the bits. The processor circuit suspends operation each time after executing a respective one of the series of instructions. A synchronization circuit triggers execution of respective ones of the series, each time at the time of reception of the respective one of the bits, and, except for a last one of the series, prior to reception of one or more later bits that contribute to the data word.

Abstract: A data processing apparatus receives a message containing a sync break interval with a unique bit pattern and a sync field interval identified by the sync break interval. A timing property of the sync field interval specifies the length of bit periods of the message. A clock source circuit supplies a sampling clock signal to define time points for sampling bits from the message. The clock source circuit adapts a frequency of the sampling clock signal to the timing property of the sync field interval.