Patents by Inventor Franciscus M. L. van der Goes

Franciscus M. L. van der Goes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High speed, low power comparator
    Patent number: 7129865
    Abstract: A method for reducing bit errors in an analog to digital converter having an array of comparators. The outputs of first and second comparators are received as in inputs to an Exclusive OR gate. The first and second comparators are separated in the array by a third comparator. The output of the Exclusive OR gate is used to determine if the third comparator is in a metastable condition. If the third comparator is in a metastable condition, the bias current of the latch circuit of the third comparator is increased to increase the rate at which the third comparator transitions to a steady state.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: October 31, 2006
    Assignee: Broadcom Corporation
    Inventors: Jan Mulder, Franciscus M. L. van der Goes
  • Method for increasing rate at which a comparator in a metastable condition transitions to a steady state
    Patent number: 6876318
    Abstract: A method for reducing bit errors in an analog to digital converter having an array of comparators. The outputs of first and second comparators are received as in inputs to an Exclusive OR gate. The first and second comparators are separated in the array by a third comparator. The output of the Exclusive OR gate is used to determine if the third comparator is in a metastable condition. If the third comparator is in a metastable condition, the bias current of the latch circuit of the third comparator is increased to increase the rate at which the third comparator transitions to a steady state.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: April 5, 2005
    Assignee: Broadcom Corporation
    Inventors: Jan Mulder, Franciscus M. L. van der Goes
  • Method for increasing rate at which a comparator in a metastable condition transitions to a steady state
    Publication number: 20040169597
    Abstract: A method for reducing bit errors in an analog to digital converter having an array of comparators. The outputs of first and second comparators are received as in inputs to an Exclusive OR gate. The first and second comparators are separated in the array by a third comparator. The output of the Exclusive OR gate is used to determine if the third comparator is in a metastable condition. If the third comparator is in a metastable condition, the bias current of the latch circuit of the third comparator is increased to increase the rate at which the third comparator transitions to a steady state.
    Type: Application
    Filed: March 12, 2004
    Publication date: September 2, 2004
    Inventors: Jan Mulder, Franciscus M.L. van der Goes
  • High speed, low power comparator
    Patent number: 6727839
    Abstract: A method for reducing bit errors in an analog to digital converter having an array of comparators. The outputs of first and second comparators are received as in inputs to an Exclusive OR gate. The first and second comparators are separated in the array by a third comparator. The output of the Exclusive OR gate is used to determine if the third comparator is in a metastable condition. If the third comparator is in a metastable condition, the bias current of the latch circuit of the third comparator is increased to increase the rate at which the third comparator transitions to a steady state.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: April 27, 2004
    Assignee: Broadcom Corporation
    Inventors: Jan Mulder, Franciscus M. L. van der Goes
  • HIGH SPEED, LOW POWER COMPARATOR
    Publication number: 20040036644
    Abstract: A method for reducing bit errors in an analog to digital converter having an array of comparators. The outputs of first and second comparators are received as in inputs to an Exclusive OR gate. The first and second comparators are separated in the array by a third comparator. The output of the Exclusive OR gate is used to determine if the third comparator is in a metastable condition. If the third comparator is in a metastable condition, the bias current of the latch circuit of the third comparator is increased to increase the rate at which the third comparator transitions to a steady state.
    Type: Application
    Filed: August 23, 2002
    Publication date: February 26, 2004
    Applicant: Broadcom Corporation
    Inventors: Jan Mulder, Franciscus M. L. van der Goes