Patents by Inventor Franciscus P. J. M. Welten

Franciscus P. J. M. Welten has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Logic full adder circuit
    Patent number: 4730266
    Abstract: A logic circuit incorporating carry look-ahead in which efficiency can be achieved regarding the hardware for generating the sum signals and carry signals by a suitable choice of the adder gate, making use of the already present signal a.sub.1 .multidot.b.sub.i which is used for generating the carry look-ahead signal.
    Type: Grant
    Filed: February 4, 1985
    Date of Patent: March 8, 1988
    Assignee: U.S. Philips Corporation
    Inventors: Jozef L. van Meerbergen, Hendrikus J. M. Veendrick, Franciscus P. J. M. Welten, Franciscus J. A. van Wijk