Abstract: A method for testing a hierarchically organized integrated circuit means first attacks each assembly in sequence thereof, and in each assembly executing an assembly test cycle. Each assembly test cycle within the assembly in question attacks each macro thereof in sequence and conditionally executes therein a test run under selective control of a macro test mode (MTM) signal. The number of hierarchy levels may be other than three. The method may be applicable to separate integrated circuits or to a wired board with a plurality of circuits.

Abstract: A memory device that contains a static RAM memory is provided with data input and data output registers, an address register, and a control register for storing various control signals. The RAM has three principal modes:a. in a normal mode, all registers are accessible externally so that the memory may fulfill its standard function,b. in a scan-state, all the cited register constitute a synchronous shift register that may be serially written with a test pattern and serially read with a result pattern; in this way the memory may be subjected to a test according to the scan test principle,c. in a self test state the communication with the outer world is shut off, the address register counts through successive addresses, the memory is cycled through read-modify or read-modify-read operations, and the data read is conversed to a signature pattern for subsequent scan-out. In this way a quasi stand-alone test facility is realized. Various additional features may be implemented.

Abstract: A method of testing an interconnection function between two integrated circuits which are mounted on a carrier and which are interconnected by data connections, for example a printed wiring board, is disclosed. The integrated circuits are also connected to a serial bus via which test patterns and result patterns can be communicated between a test device which can be connected thereto and the respective integrated circuits. The bus of a preferred embodiment is formed by a so-called I.sup.2 C bus. In a further elaboration, this set-up can also be used for testing the internal logic circuitry of the integrated circuits. For the testing of the interconnection function, input/output cells with a parallel connection for performing the normal execution function in a transparent mode are provided. They also include series connections for communication test/result patterns by way of a shift register.

Abstract: A modified Booth multiplier for multiplying an m-bit number X by an n-bit number Y comprises a Booth encoder for converter the number Y in groups of 3 bits which overlap by 1 bit into a series Y' of multiplication values whose number is equal to or substantially equal to half the number of bits of Y. There is also provided a multiplex circuit for forming partial products from the number X and said series Y' and a matrix configuration of full adders for adding the partial products in incremental positions. The design is such that the constituent components and the operation of the modified Booth multiplier can be tested by means of a very small number of test patterns which are generated in the Booth multiplier after application of a specific series of X,Y-values.

Abstract: A method of testing an interconnection function between two integrated circuits which are mounted on a carrier and which are interconnected by data connections, for example a printed wiring board, is disclosed. The integrated circuits are also connected to a serial bus via which test patterns and result patterns can be communicated between a test device which can be connected thereto and the respective integrated circuits. The bus of a preferred embodiment is formed by a so-called I.sup.2 C bus. In a further elaboration, this set-up can also be used for testing the internal logic circuitry of the integrated circuits. For the testing of the interconnection function, input/output cells with a parallel connection for performing the normal execution function in a transparent mode are provided. They also include series connections for communication test/result patterns by way of a shift register.