Abstract: A capacitive pressure sensor for a pressure-sensing guidewire or catheter includes a substrate; a first active cell formed in the substrate; a second active cell formed in the substrate, wherein the first active cell and the second active cell are electrically active to generate electrical signals representative of an external pressure; and an optional dummy cell formed in the substrate, wherein the dummy cell is electrically inactive such that no electrical signal representative of the external pressure is generated. An intraluminal pressure-sensing device and a system are also provided.

Abstract: A flexible conductive track arrangement has a pre-flexing condition in which the arrangement is generally planar. Conductive tracks are formed from a metal layer and they are covered above and below by insulator layers. The elongate conductive tracks are generally planar but locally corrugated perpendicularly to the general plane. This enables improved binding performance, for example to form tight windings using the conductive tracks.

Abstract: A flexible conductive track arrangement has a pre-flexing condition in which the arrangement is generally planar. Conductive tracks are formed from a metal layer and they are covered above and below by insulator layers. The elongate conductive tracks are generally planar but locally corrugated perpendicularly to the general plane. This enables improved binding performance, for example to form tight windings using the conductive tracks.

Abstract: A photovoltaic device, having an improved passivation of surfaces, such as a circumferential outer wall and/or an aperture wall of a back contact metal wrap-through photovoltaic device, for example, into which the pn-junction of first and second semiconductor layers extends. The passivation comprises a passivating layer of a first type, covering at least part of such wall substantially comprised by the depletion region across the pn-junction; a passivating layer of a second type, covering at least part of such wall comprised by the first semiconductor layer, and a passivating layer of a third type covering at least part of the outer wall comprised by the second semiconductor layer.