Patents by Inventor Franciscus Wilhelmus Sijstermans

Franciscus Wilhelmus Sijstermans has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10096134
    Abstract: A method, computer program product, and system for sparse convolutional neural networks that improves efficiency is described. Multi-bit data for input to a processing element is received at a compaction engine. The multi-bit data is determined to equal zero and a single bit signal is transmitted from the memory interface to the processing element in lieu of the multi-bit data, where the single bit signal indicates that the multi-bit data equals zero. A compacted data sequence for input to a processing element is received by a memory interface. The compacted data sequence is transmitted from the memory interface to an expansion engine. Non-zero values are extracted from the compacted data sequence and zeros are inserted between the non-zero values by the expansion engine to generate an expanded data sequence that is output to the processing element.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: October 9, 2018
    Assignee: NVIDIA Corporation
    Inventors: Zhou Yan, Franciscus Wilhelmus Sijstermans, Yuanzhi Hua, Xiaojun Wang, Jeffrey Michael Pool, William J. Dally, Liang Chen
  • Publication number: 20180218518
    Abstract: A method, computer program product, and system for sparse convolutional neural networks that improves efficiency is described. Multi-bit data for input to a processing element is received at a compaction engine. The multi-bit data is determined to equal zero and a single bit signal is transmitted from the memory interface to the processing element in lieu of the multi-bit data, where the single bit signal indicates that the multi-bit data equals zero. A compacted data sequence for input to a processing element is received by a memory interface. The compacted data sequence is transmitted from the memory interface to an expansion engine. Non-zero values are extracted from the compacted data sequence and zeros are inserted between the non-zero values by the expansion engine to generate an expanded data sequence that is output to the processing element.
    Type: Application
    Filed: February 1, 2017
    Publication date: August 2, 2018
    Inventors: Zhou Yan, Franciscus Wilhelmus Sijstermans, Yuanzhi Hua, Xiaojun Wang, Jeffrey Michael Pool, William J. Dally, Liang Chen