Patents by Inventor Franck Dahan

Franck Dahan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190021054
    Abstract: Methods, systems, and devices for wireless communication are described. A user equipment (UE) may be enabled for voice over long term evolution (VoLTE). The UE may include an audio layer to encode and decode voice information and a packet layer to transmit voice packets. The packet layer may store parameters related to a discontinuous reception (DRX) in a shared memory. The audio layer may obtain the DRX parameters and encode voice information based on the parameters. For example, the audio layer coding may be synchronized with the wake period of the DRX cycle. The audio layer may encode voice information during a wake up period of the packet layer DRX cycle, and the packet layer may transmit the voice packets while awake. The audio layer may perform back to back encodings at the beginning of the DRX cycle. The packet layer may extend the wake period to transmit the voice packets.
    Type: Application
    Filed: October 2, 2017
    Publication date: January 17, 2019
    Inventors: Ping Zhou, Sudhir Krishnan, Prashanth Gurram, Kunal Atitkar, Franck Dahan, Xin Kang
  • Patent number: 8458429
    Abstract: An apparatus and method for dynamically modifying one or more operating conditions of a memory controller in an electronic device. Operating conditions may comprise clock frequency and power, which may be modified or removed. Dynamic modification of operating conditions may be done for purposes of optimizing a parameter, such as power consumption. A mode, referred to as idle mode, may be used as a transitional or operational mode for the memory controller. The performance of the memory controller may dynamically vary in response to changes in its operating conditions. As such, the memory controller may comprise multiple modes, or submodes, of operation. The performance of the memory controller may depend on the type of memory it controls, for instance Double Data Rate (DDR) Dynamic Random Access Memory (DRAM).
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: June 4, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Franck Dahan, Gilles Dubost, Sylvain Dubois
  • Patent number: 8278980
    Abstract: An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: October 2, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Gilles Dubost, Franck Dahan, Hugh Thomas Mair, Sylvain Dubois
  • Publication number: 20120235716
    Abstract: An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop.
    Type: Application
    Filed: May 31, 2012
    Publication date: September 20, 2012
    Inventors: GILLES DUBOST, Franck Dahan, Hugh Thomas Mair, Sylvain Dubois
  • Patent number: 8207764
    Abstract: An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: June 26, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Gilles Dubost, Franck Dahan, Hugh Thomas Mair, Sylvain Dubois
  • Patent number: 8117367
    Abstract: A processor system with an application and a maintenance function that would interfere with the application if concurrently executed. The processor system comprises a set of processor cores operable in different security and context-related modes, said processors having at least one interrupt input and at least one wait for interrupt output. The processor system also comprises a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processor cores operable in response to the interrupt signal to schedule a maintenance function separated in time from execution of the application.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: February 14, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory R. Conti, Franck Dahan
  • Patent number: 8069290
    Abstract: A processing system operable in various execution environments. The system comprises plural processor cores having respective interrupt inputs, respective wait for interrupt outputs, and respective security outputs. The system also comprises a register coupled to at least one of the processor cores for identifying active execution environments. The system also comprises a global interrupt handler operable to selectively route interrupts to one or more of the interrupt inputs of said plural processor cores. The system also comprises a conversion circuit having plural interrupt-related output lines, and said conversion circuit fed with at least some of said respective wait for interrupt outputs and respective security outputs and fed by said register.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: November 29, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory R. Conti, Franck Dahan
  • Patent number: 8055828
    Abstract: An electronic power management system comprising plural processors operable in different security and context-related modes and having respective supply voltage inputs and clock inputs, said processors having at least one interrupt input and at least one wait for interrupt output. The system further comprises a power control circuit operable to configurably adjust supply voltages and clock rates for said supply voltage inputs and clock inputs. The system further comprises a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processors operable to configure said power control circuit in response to the interrupt signal.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: November 8, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory R. Conti, Franck Dahan
  • Publication number: 20110173363
    Abstract: A processor system with an application and a maintenance function that would interfere with the application if concurrently executed. The processor system comprises a set of processor cores operable in different security and context-related modes, said processors having at least one interrupt input and at least one wait for interrupt output. The processor system also comprises a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processor cores operable in response to the interrupt signal to schedule a maintenance function separated in time from execution of the application.
    Type: Application
    Filed: February 16, 2011
    Publication date: July 14, 2011
    Applicant: TEXAS INSTRUMENTS INCOPORATED
    Inventors: Gregory Conti, Franck Dahan
  • Publication number: 20110145459
    Abstract: An electronic power management system comprising plural processors operable in different security and context-related modes and having respective supply voltage inputs and clock inputs, said processors having at least one interrupt input and at least one wait for interrupt output. The system further comprises a power control circuit operable to configurably adjust supply voltages and clock rates for said supply voltage inputs and clock inputs. The system further comprises a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processors operable to configure said power control circuit in response to the interrupt signal.
    Type: Application
    Filed: February 16, 2011
    Publication date: June 16, 2011
    Applicant: TEXAS INSTRUMENTS INCOPORATED
    Inventors: Gregory Conti, Franck Dahan
  • Publication number: 20110145460
    Abstract: A processing system operable in various execution environments. The system comprises plural processor cores having respective interrupt inputs, respective wait for interrupt outputs, and respective security outputs. The system also comprises a register coupled to at least one of the processor cores for identifying active execution environments. The system also comprises a global interrupt handler operable to selectively route interrupts to one or more of the interrupt inputs of said plural processor cores. The system also comprises a conversion circuit having plural interrupt-related output lines, and said conversion circuit fed with at least some of said respective wait for interrupt outputs and respective security outputs and fed by said register.
    Type: Application
    Filed: February 16, 2011
    Publication date: June 16, 2011
    Applicant: TEXAS INSTRUMENTS INCOPORATED
    Inventors: Gregory Conti, Franck Dahan
  • Publication number: 20110095794
    Abstract: An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop.
    Type: Application
    Filed: October 28, 2009
    Publication date: April 28, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gilles Dubost, Franck Dahan, Hugh Thomas Mair, Sylvain Dubois
  • Patent number: 7934036
    Abstract: An electronic interrupt circuit includes an interrupt-related input line, a security-related status input line, a context-related status input line, and a conversion circuit having plural interrupt-related output lines and selectively operable in response to an interrupt-related signal on said interrupt-related input line depending on an active or inactive status of each of said security-related status input line and said context-related status input line.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: April 26, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory Conti, Franck Dahan
  • Patent number: 7890753
    Abstract: A digital system is provided with a secure mode (3rd level of privilege) built in a non-invasive way on a processor system that includes a processor core, instruction and data caches, a write buffer and a memory management unit. A secure execution mode is thus provided on a platform where the only trusted software is the code stored in ROM. In particular the OS is not trusted, all native applications are not trusted. A secure execution mode is provided that allows virtual addressing when a memory management unit (MMU) is enabled. The secure execution mode allows instruction and data cache to be enabled. A secure execution mode is provided that allows all the system interruptions to be unmasked. The secure mode is entered through a unique entry point. The secure execution mode can be dynamically entered and exited with full hardware assessment of the entry/exit conditions. A specific set of entry conditions is monitored that account for caches, write buffer and MMU being enabled.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: February 15, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Franck Dahan, Christian Roussel, Alain Chateau, Peter Cumming
  • Patent number: 7840827
    Abstract: An apparatus and method for power management of a display system. A display controller couples to a memory storage device. A frame buffer in the memory storage device is filled with frames of information for display on a display device. The frames of information transfer to a display buffer in the display controller. The display controller transmits the frames of information from the display buffer to the display device. When frame information is not being transferred to the display controller, the display controller and the memory storage device may separately enter a power saving state. In power saving state, the display controller may continue to transmit frame information to the display device; however, power and a clock signal to components of display controller may be limited. When the display buffer is almost empty, the display controller exits power saving state to fill the display buffer.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: November 23, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Franck Dahan, Franck Seigneret, Gilles Dubost, Jean Noel
  • Patent number: 7809961
    Abstract: An apparatus and method for controlling standby mode in an electronic device. In standby mode, power and clock signals are reduced or stopped to conserve power. The apparatus includes an initiator module coupled to a power and clock control module (PCCM). When the initiator module meets conditions for standby mode, the initiator module sends a standby signal to the PCCM and does not interact with other initiator, target, or interconnect modules. When the PCCM communicates a wait signal, the initiator module enters standby mode. When the initiator module detects a wakeup event, the standby signal is deactivated. In this state, the initiator module may process information but may not interact with other modules. When the PCCM deactivates the wait signal and returns power and clock signal to steady state levels, initiator module may resume normal operation.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: October 5, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Franck Dahan, Franck Seigneret, Gilles Dubost
  • Patent number: 7587525
    Abstract: An apparatus and method for conserving power in a memory information transfer system. The system may include a direct memory access (DMA) controller coupled to a memory storage device and a peripheral device. The DMA controller transfers information from the memory storage device to a buffer in the peripheral device. The DMA controller may also transfer information from the buffer in the peripheral device to the memory storage device. When the peripheral device buffer does not have to be filled or emptied by the DMA controller, the DMA controller enters a standby mode. When the peripheral device buffer is full or empty, the DMA controller exits standby mode, empties or fills the peripheral device buffer, and reenters standby mode.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: September 8, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Franck Dahan, Franck Seigneret, Gilles Dubost
  • Publication number: 20090049220
    Abstract: An electronic interrupt circuit includes an interrupt-related input line (4235), a security-related status input line (4236), a context-related status input line (4237), and a conversion circuit (4234A) having plural interrupt-related output lines (4245) and selectively operable in response to an interrupt-related signal on said interrupt-related input line (4235) depending on an active or inactive status of each of said security-related status input line (4236) and said context-related status input line (4237).
    Type: Application
    Filed: April 10, 2008
    Publication date: February 19, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gregory Conti, Franck Dahan
  • Publication number: 20080307240
    Abstract: An electronic circuit including a power managed circuit (2610), and a power management control circuit (3570) coupled to the power managed circuit (2610) and operable to select between at least a first operating performance point (OPP1) and a second higher operating performance point (OPP2) for the power managed circuit (2610), each performance point including a respective pair (Vn, Fn) of voltage and operating frequency, and the power management control circuit (3570) further operable to control dynamic power switching of the power managed circuit (2610) based on a condition wherein the power managed circuit (2610) at a given operating performance point has a static power dissipation (4820.1), and the dynamic power switching puts the power managed circuit in a lower static power state (4860.1) that dissipates less power than the static power dissipation (4820.1).
    Type: Application
    Filed: June 8, 2007
    Publication date: December 11, 2008
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Franck Dahan, Gilles Dubost, Gordon Gammie, Uming Ko, Hugh Mair, Sang-Won Song, Alice Wang, William D. Wilson
  • Publication number: 20080162980
    Abstract: An apparatus and method for dynamically modifying one or more operating conditions of a memory controller in an electronic device. Operating conditions may comprise clock frequency and power, which may be modified or removed. Dynamic modification of operating conditions may be done for purposes of optimizing a parameter, such as power consumption. A mode, referred to as idle mode, may be used as a transitional or operational mode for the memory controller. The performance of the memory controller may dynamically vary in response to changes in its operating conditions. As such, the memory controller may comprise multiple modes, or submodes, of operation. The performance of the memory controller may depend on the type of memory it controls, for instance Double Data Rate (DDR) Dynamic Random Access Memory (DRAM).
    Type: Application
    Filed: November 30, 2007
    Publication date: July 3, 2008
    Inventors: Franck Dahan, Gilles Dubost, Sylvain Dubois