Patents by Inventor Franck Galtié
Franck Galtié has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240020786Abstract: An event manager for filtering safety and security events of a system including an event sequence list including predetermined event sequences in which each sequence includes at least one event identifier identifying a corresponding one of multiple monitored events, an event sequence array that stores a received event sequence in response to received event notifications, and a controller that stores an event identifier into the event sequence array and that determines whether the received event sequence matches at least one of the predetermined event sequences for determining a composite event and a response for each received event notification. The matching determination may be made with or without consideration of chronological order. A suspected composite event may be identified when multiple possible matches may exist, and a final composite event is ratified when only one match is found. An exception may be generated upon timeout of a timer.Type: ApplicationFiled: July 13, 2023Publication date: January 18, 2024Inventors: Andres Barrilado Gonzalez, Franck Galtie, Rolf Dieter Schlagenhaft, Hemant Nautiyal
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Publication number: 20230171293Abstract: An architecture for monitoring, analyzing, and reacting to safety and cybersecurity events has been disclosed. In at least one embodiment, a method for processing safety and security events of a system includes requesting a reaction or escalating an effect from a first controller of the system to a second controller of the system based on a subset of available reactions for a current context of the system, constraint information, a predetermined effect-reaction policy, and the effect.Type: ApplicationFiled: November 20, 2022Publication date: June 1, 2023Inventors: Franck Galtie, Rolf Dieter Schlagenhaft, Andres Barrilado Gonzalez
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Patent number: 9658664Abstract: An electronic device having a pin for setting its mode of operation, wherein the pin is connected or connectable to a first connection of a resistor, wherein the electronic device is arranged to detect a location of the resistor, wherein the electronic device is arranged to detect a size of the resistor, wherein the electronic device is arranged to determine a first setting based on the location of the resistor, and wherein the electronic device is arranged to determine a second setting based on the size of the resistor.Type: GrantFiled: April 26, 2012Date of Patent: May 23, 2017Assignee: NXP USA, Inc.Inventors: Valerie Bernon-Enjalbert, Philippe Mounier, Franck Galtie
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Patent number: 9484811Abstract: An integrated circuit comprising voltage modulation circuitry arranged to convert an input voltage level at an input node to an output voltage level at an output node. The voltage modulation circuitry comprises a switching element arranged to connect the input node to the output node when in an ON condition, and switching control module operably coupled to the switching element and arranged to control the connection of the input node to the output node by the switching element in accordance with a switching frequency. The voltage modulation circuitry further comprises frequency control module operably coupled to the switching control module and arranged to receive an indication of the input voltage level at the input node, and to configure the switching frequency based at least partly on the input voltage level indication.Type: GrantFiled: July 16, 2009Date of Patent: November 1, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Franck Galtie, Philippe Goyhenetche, Eric Rolland
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Patent number: 9425692Abstract: A DC to DC converter including a buck converter, a boost converter, and a control unit, wherein the control unit is arranged to calculate an error voltage of the buck converter Verr_buck based on a feedback output voltage Vout_FB of the DC to DC converter and a reference voltage of the buck converter Vref_buck, and wherein the control unit is arranged to calculate an error voltage of the boost converter Verr_boost based on the feedback output voltage Vout_FB of the DC to DC converter and a reference voltage of the boost converter Vref_boost, wherein the reference voltage of the boost converter Vref_boost is shifted by an offset Voffset as compared to the reference voltage of the buck converter Vref_buck.Type: GrantFiled: January 20, 2012Date of Patent: August 23, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Valerie Bernon-Enjalbert, Franck Galtie, Philippe Goyhenetche
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Publication number: 20150082017Abstract: An electronic device having a pin for setting its mode of operation, wherein the pin is connected or connectable to a first connection of a resistor, wherein the electronic device is arranged to detect a location of the resistor, wherein the electronic device is arranged to detect a size of the resistor, wherein the electronic device is arranged to determine a first setting based on the location of the resistor, and wherein the electronic device is arranged to determine a second setting based on the size of the resistor.Type: ApplicationFiled: April 26, 2012Publication date: March 19, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Valerie Bernon-Enjalbert, Philippe Mounier, Franck Galtie
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Publication number: 20150002116Abstract: A DC to DC converter including a buck converter, a boost converter, and a control unit, wherein the control unit is arranged to calculate an error voltage of the buck converter Verr_buck based on a feedback output voltage Vout_FB of the DC to DC converter and a reference voltage of the buck converter Vref_buck, and wherein the control unit is arranged to calculate an error voltage of the boost converter Verr_boost based on the feedback output voltage Vout_FB of the DC to DC converter and a reference voltage of the boost converter Vref_boost, wherein the reference voltage of the boost converter Vref_boost is shifted by an offset Voffset as compared to the reference voltage of the buck converter Vref_buck.Type: ApplicationFiled: January 20, 2012Publication date: January 1, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Valerie Bernon-Enjalbert, Franck Galtie, Philippe Goyhenetche
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Publication number: 20120098510Abstract: An integrated circuit comprising voltage modulation circuitry arranged to convert an input voltage level at an input node to an output voltage level at an output node. The voltage modulation circuitry comprises a switching element arranged to connect the input node to the output node when in an ON condition, and switching control module operably coupled to the switching element and arranged to control the connection of the input node to the output node by the switching element in accordance with a switching frequency. The voltage modulation circuitry further comprises frequency control module operably coupled to the switching control module and arranged to receive an indication of the input voltage level at the input node, and to configure the switching frequency based at least partly on the input voltage level indication.Type: ApplicationFiled: July 16, 2009Publication date: April 26, 2012Applicant: Freescale Semiconductor, Inc.Inventors: Franck Galtie, Philippe Goyhenetche, Eric Rolland
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Patent number: 7710699Abstract: A method and a circuit for limiting the current in an inductance, comprising means for interrupting the power storage in the inductance at the end of a delay triggered by the current in the inductance.Type: GrantFiled: December 14, 2004Date of Patent: May 4, 2010Assignee: STMicroelectronics SAInventors: Arnaud Florence, Jérome Heurtier, Franck Galtie
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Patent number: 7170768Abstract: A controllable rectifying element, comprising a bipolar transistor having a current input terminal connected to a control terminal by a first switch and having a current output terminal connected to the control terminal by a second switch, the turn-off and turn-on phases of the first and second switches being complementary and depending on the state desired for the rectifying element.Type: GrantFiled: December 3, 2003Date of Patent: January 30, 2007Assignee: STMicroelectronics S.A.Inventors: Jérôme Heurtier, Arnaud Florence, Franck Galtié
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Patent number: 6920054Abstract: A generator of at least one pulse width modulated signal, including: a generator of a sawtooth signal a generator of high and low reference signals defining, based on a set-point signal, a linear range of each ramp of the sawtooth signal at least one element of comparison of the sawtooth signal with each of the reference signals and at least one element of logic combination of the comparison results, providing the pulse width modulated signal.Type: GrantFiled: December 4, 2003Date of Patent: July 19, 2005Assignee: STMicroelectronics S.A.Inventors: Arnaud Florence, Jérôme Heurtier, Franck Galtie
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Publication number: 20050135128Abstract: A method and a circuit for limiting the current in an inductance, comprising means for interrupting the power storage in the inductance at the end of a delay triggered by the current in the inductance.Type: ApplicationFiled: December 14, 2004Publication date: June 23, 2005Inventors: Arnaud Florence, Jerome Heurtier, Franck Galtie
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Publication number: 20040119452Abstract: A generator of at least one pulse width modulated signal, including: a generator of a sawtooth signal a generator of high and low reference signals defining, based on a set-point signal, a linear range of each ramp of the sawtooth signal at least one element of comparison of the sawtooth signal with each of the reference signals and at least one element of logic combination of the comparison results, providing the pulse width modulated signal.Type: ApplicationFiled: December 4, 2003Publication date: June 24, 2004Applicant: STMicroelectronics S.A.Inventors: Arnaud Florence, Jerome Heurtier, Franck Galtie
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Publication number: 20040109336Abstract: A controllable rectifying element, comprising a bipolar transistor having a current input terminal connected to a control terminal by a first switch and having a current output terminal connected to the control terminal by a second switch, the turn-off and turn-on phases of the first and second switches being complementary and depending on the state desired for the rectifying element.Type: ApplicationFiled: December 3, 2003Publication date: June 10, 2004Applicant: STMicroelectronics S.A.Inventors: Jerome Heurtier, Arnaud Florence, Franck Galtie
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Patent number: 6583496Abstract: A monolithic component including two thyristors of a composite bridge connected to an A.C. voltage terminal by a common terminal corresponding to a common rear surface metallization forming an electrode of opposite biasing of each thyristor. An isolating wall separates a substrate in two portions, a first portion includes on its lower surface side an anode region and on its upper surface side a cathode region, the second portion includes on its lower surface side a cathode region and on its upper surface side an anode region. The isolating wall surrounding each of the components extending towards the main electrode on the side which carries no common metallization and including in this extended region an N-type area, the two areas being connected together to a common control terminal.Type: GrantFiled: May 2, 2001Date of Patent: June 24, 2003Assignee: STMicroelectronics S.A.Inventors: Franck Galtie, Olivier Ladiray
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Publication number: 20020008247Abstract: A monolithic component including two thyristors of a composite bridge connected to an A.C. voltage terminal by a common terminal corresponding to a common rear surface metallization forming an electrode of opposite biasing of each thyristor. An isolating wall separates a substrate in two portions, a first portion includes on its lower surface side an anode region and on its upper surface side a cathode region, the second portion includes on its lower surface side a cathode region and on its upper surface side an anode region. The isolating wall surrounding each of the components extending towards the main electrode on the side which carries no common metallization and including in this extended region an N-type area, the two areas being connected together to a common control terminal.Type: ApplicationFiled: May 2, 2001Publication date: January 24, 2002Inventors: Franck Galtie, Olivier Ladiray