Patents by Inventor Franck Lunadier
Franck Lunadier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220107904Abstract: A bus architecture is disclosed that provides for transaction queue reallocation on the modules communicating using the bus. A module can implement a transaction request queue by virtue of digital electronic circuitry, e.g., hardware or software or a combination of both. Some bus clogging issues that affect conventional systems can be circumvented by combining an out of order system bus protocol that uses a transaction request replay mechanism. Modules can evict less urgent transactions from transaction request queues to make room to insert more urgent transactions. Master modules can dynamically update a quality of service (QoS) value for a transaction while the transaction is still pending.Type: ApplicationFiled: December 14, 2021Publication date: April 7, 2022Inventors: Franck Lunadier, Vincent Debout
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Patent number: 11256632Abstract: A bus architecture is disclosed that provides for transaction queue reallocation on the modules communicating using the bus. A module can implement a transaction request queue by virtue of digital electronic circuitry, e.g., hardware or software or a combination of both. Some bus clogging issues that affect conventional systems can be circumvented by combining an out of order system bus protocol that uses a transaction request replay mechanism. Modules can evict less urgent transactions from transaction request queues to make room to insert more urgent transactions. Master modules can dynamically update a quality of service (QoS) value for a transaction while the transaction is still pending.Type: GrantFiled: September 14, 2016Date of Patent: February 22, 2022Assignee: Atmel CorporationInventors: Franck Lunadier, Vincent Debout
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Patent number: 9898362Abstract: Systems, methods, circuits and computer-readable mediums for multi-channel RAM system with error-correcting code (ECC) protection for partial writes are provided. In one aspect, a method includes accessing a plurality of bursts of partial data units from a plurality of respective bus ports, forming a plurality of memory addresses for a plurality of memory channels by interleaving addresses from the plurality of bus ports, and performing read-modify-write (RMW) error-correcting code (ECC) processes to write partial data units from the plurality of bursts into memory portions corresponding to the formed memory addresses in the plurality of memory channels.Type: GrantFiled: April 7, 2016Date of Patent: February 20, 2018Assignee: Atmel CorporationInventor: Franck Lunadier
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Publication number: 20170293523Abstract: Systems, methods, circuits and computer-readable mediums for multi-channel RAM system with error-correcting code (ECC) protection for partial writes are provided. In one aspect, a method includes accessing a plurality of bursts of partial data units from a plurality of respective bus ports, forming a plurality of memory addresses for a plurality of memory channels by interleaving addresses from the plurality of bus ports, and performing read-modify-write (RMW) error-correcting code (ECC) processes to write partial data units from the plurality of bursts into memory portions corresponding to the formed memory addresses in the plurality of memory channels.Type: ApplicationFiled: April 7, 2016Publication date: October 12, 2017Inventor: Franck Lunadier
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Publication number: 20170017593Abstract: A multi-matrix bus system is disclosed that provides proactive quality of service (QoS) by propagating, as soon as possible through an arbitration node in a network transfer request path, a highest priority value coming from an upstream arbitration node or master that has a current bus request pending at the arbitration node. The bus system ensures that any last downstream arbitration node knows at any time which is the highest priority request pending in the network transfer request path from the masters that are competing to share the bus layer switches and arbitration nodes in the network transfer request path.Type: ApplicationFiled: June 20, 2016Publication date: January 19, 2017Applicant: Atmel CorporationInventors: Franck Lunadier, Eric Matulik, Renaud Tiennot
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Publication number: 20170004097Abstract: A bus architecture is disclosed that provides for transaction queue reallocation on the modules communicating using the bus. A module can implement a transaction request queue by virtue of digital electronic circuitry, e.g., hardware or software or a combination of both. Some bus clogging issues that affect conventional systems can be circumvented by combining an out of order system bus protocol that uses a transaction request replay mechanism. Modules can evict less urgent transactions from transaction request queues to make room to insert more urgent transactions. Master modules can dynamically update a quality of service (QoS) value for a transaction while the transaction is still pending.Type: ApplicationFiled: September 14, 2016Publication date: January 5, 2017Inventors: Franck Lunadier, Vincent Debout
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Patent number: 9471524Abstract: A bus architecture is disclosed that provides for transaction queue reallocation on the modules communicating using the bus. A module can implement a transaction request queue by virtue of digital electronic circuitry, e.g., hardware or software or a combination of both. Some bus clogging issues that affect conventional systems can be circumvented by combining an out of order system bus protocol that uses a transaction request replay mechanism. Modules can evict less urgent transactions from transaction request queues to make room to insert more urgent transactions. Master modules can dynamically update a quality of service (QoS) value for a transaction while the transaction is still pending.Type: GrantFiled: December 9, 2013Date of Patent: October 18, 2016Assignee: Atmel CorporationInventors: Franck Lunadier, Vincent Debout
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Patent number: 9372818Abstract: A multi-matrix bus system is disclosed that provides proactive quality of service (QoS) by propagating, as soon as possible through an arbitration node in a network transfer request path, a highest priority value coming from an upstream arbitration node or master that has a current bus request pending at the arbitration node. The bus system ensures that any last downstream arbitration node knows at any time which is the highest priority request pending in the network transfer request path from the masters that are competing to share the bus layer switches and arbitration nodes in the network transfer request path.Type: GrantFiled: March 15, 2013Date of Patent: June 21, 2016Assignee: Atmel CorporationInventors: Franck Lunadier, Eric Matulik, Renaud Tiennot
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Patent number: 9317462Abstract: A system includes one or more master modules configured to execute instructions embedded in non-transitory machine-readable media and controllable by a processor. The system also includes one or more peripheral modules that are configured to execute instructions embedded in non-transitory machine-readable media and controllable by the processor. The system also includes a system bus with instructions embedded in a non-transitory machine-readable medium and configured to allow data transfer between the processor and the one or more peripheral modules. A data processing module of the one or more peripheral modules includes a master interface and a slave interface. Both master and slave interfaces are coupled to the system bus.Type: GrantFiled: March 16, 2015Date of Patent: April 19, 2016Assignee: Atmel CorporationInventors: Guillaume Pean, Franck Lunadier, Alain Vergnes
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Publication number: 20150186314Abstract: A system includes one or more master modules configured to execute instructions embedded in non-transitory machine-readable media and controllable by a processor. The system also includes one or more peripheral modules that are configured to execute instructions embedded in non-transitory machine-readable media and controllable by the processor. The system also includes a system bus with instructions embedded in a non-transitory machine-readable medium and configured to allow data transfer between the processor and the one or more peripheral modules. A data processing module of the one or more peripheral modules includes a master interface and a slave interface. Both master and slave interfaces are coupled to the system bus.Type: ApplicationFiled: March 16, 2015Publication date: July 2, 2015Inventors: Guillaume Pean, Franck Lunadier, Alain Vergnes
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Publication number: 20150161065Abstract: A bus architecture is disclosed that provides for transaction queue reallocation on the modules communicating using the bus. A module can implement a transaction request queue by virtue of digital electronic circuitry, e.g., hardware or software or a combination of both. Some bus clogging issues that affect conventional systems can be circumvented by combining an out of order system bus protocol that uses a transaction request replay mechanism. Modules can evict less urgent transactions from transaction request queues to make room to insert more urgent transactions. Master modules can dynamically update a quality of service (QoS) value for a transaction while the transaction is still pending.Type: ApplicationFiled: December 9, 2013Publication date: June 11, 2015Inventors: FRANCK LUNADIER, VINCENT DEBOUT
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Patent number: 8984195Abstract: A system includes one or more master modules configured to execute instructions embedded in non-transitory machine-readable media and controllable by a processor. The system also includes one or more peripheral modules that are configured to execute instructions embedded in non-transitory machine-readable media and controllable by the processor. The system also includes a system bus with instructions embedded in a non-transitory machine-readable medium and configured to allow data transfer between the processor and the one or more peripheral modules. A data processing module of the one or more peripheral modules includes a master interface and a slave interface. Both master and slave interfaces are coupled to the system bus.Type: GrantFiled: December 2, 2011Date of Patent: March 17, 2015Assignee: Atmel CorporationInventors: Alain Vergnes, Franck Lunadier, Guillaume Pean
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Publication number: 20140281081Abstract: A multi-matrix bus system is disclosed that provides proactive quality of service (QoS) by propagating, as soon as possible through an arbitration node in a network transfer request path, a highest priority value coming from an upstream arbitration node or master that has a current bus request pending at the arbitration node. The bus system ensures that any last downstream arbitration node knows at any time which is the highest priority request pending in the network transfer request path from the masters that are competing to share the bus layer switches and arbitration nodes in the network transfer request path.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Franck Lunadier, Eric Matulik, Renaud Tiennot
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Patent number: 8516167Abstract: A system includes master modules, at least one multiport slave module, and a scheduler connected by a system bus. The scheduler is configured to provide scheduling information to the multiport slave module. The scheduling information includes master categorization information and anticipated burst information. The anticipated burst information is based on a scheduler determination for an anticipated bus access by an anticipated master module. The master categorization information categorizes the anticipated master.Type: GrantFiled: August 3, 2011Date of Patent: August 20, 2013Assignee: Atmel CorporationInventor: Franck Lunadier
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Patent number: 8484436Abstract: A memory controller is configured to receive read requests from a processor and return memory words from memory. The memory controller comprises an address comparator and a loop entry cache. The address comparator is configured to determine a difference between a previous read request address and a current read request address. The address comparator is also configured to determine whether the difference is positive and less than a certain address difference and, if so, indicate a limited backwards jump. The loop entry cache is configured to store a current memory word for the current read request address when the address comparator indicates a limited backwards jump.Type: GrantFiled: September 2, 2010Date of Patent: July 9, 2013Assignee: Atmel CorporationInventors: Franck Lunadier, Frédéric Schumacher
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Publication number: 20130145063Abstract: A system includes one or more master modules configured to execute instructions embedded in non-transitory machine-readable media and controllable by a processor. The system also includes one or more peripheral modules that are configured to execute instructions embedded in non-transitory machine-readable media and controllable by the processor. The system also includes a system bus with instructions embedded in a non-transitory machine-readable medium and configured to allow data transfer between the processor and the one or more peripheral modules. A data processing module of the one or more peripheral modules includes a master interface and a slave interface. Both master and slave interfaces are coupled to the system bus.Type: ApplicationFiled: December 2, 2011Publication date: June 6, 2013Applicant: Atmel Rousset S.A.S.Inventors: Alain Vergnes, Franck Lunadier, Guillaume Pean
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Publication number: 20130036246Abstract: A system includes master modules, at least one multiport slave module, and a scheduler connected by a system bus. The scheduler is configured to provide scheduling information to the multiport slave module. The scheduling information includes master categorization information and anticipated burst information. The anticipated burst information is based on a scheduler determination for an anticipated bus access by an anticipated master module. The master categorization information categorizes the anticipated master.Type: ApplicationFiled: August 3, 2011Publication date: February 7, 2013Applicant: ATMEL ROUSSET S.A.S.Inventor: Franck Lunadier
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Publication number: 20120059975Abstract: A memory controller is configured to receive read requests from a processor and return memory words from memory. The memory controller comprises an address comparator and a loop entry cache. The address comparator is configured to determine a difference between a previous read request address and a current read request address. The address comparator is also configured to determine whether the difference is positive and less than a certain address difference and, if so, indicate a limited backwards jump. The loop entry cache is configured to store a current memory word for the current read request address when the address comparator indicates a limited backwards jump.Type: ApplicationFiled: September 2, 2010Publication date: March 8, 2012Applicant: ATMEL ROUSSET S.A.S.Inventors: Franck Lunadier, Frédéric Schumacher