Abstract: The present description concerns an electronic method and device comprising a memory cell comprising a first semiconductor well of a first conductivity type, a second semiconductor well of the first conductivity type, a first layer on a lower surface of the first and second wells, an insulated conductive wall separating the first and second wells, a third semiconductor well of the second conductivity type located in the first well, a fourth semiconductor well of the second conductivity type located in the second well, and a stack of layers extending over the first and second wells and the wall, the stack comprising a second insulating layer, a third floating gate layer, a fourth insulating layer, and a fifth control gate layer.

Abstract: In an embodiment a memory cell includes a first doped well of a first conductivity type embedded in a second doped well of a second conductivity type, the second conductivity type being opposite to the first conductivity type, a third doped well of the second conductivity type embedded in a fourth doped well of the first conductivity type, a first wall in contact with the second and fourth doped wells, the first wall including a conductive or semiconductor core and an insulating liner, the insulating liner extending between the conductive or semiconductor core and the second and fourth doped wells, and a stack of layers comprising a first insulating layer, a first semiconductor layer, a second insulating layer and a second semiconductor layer, the first insulating layer being in contact with the second and fourth doped wells.

Abstract: The non-volatile memory device includes memory cells including a control gate vertically buried in a semiconductor substrate doped with a first type of dopant and a dielectric interface able to trap electrical charges covering sides of the control gate facing the semiconductor substrate. The device furthermore includes a vertical implanted region of a second type of dopant opposite to the first type located along the sides of the control gate in the semiconductor substrate.

Abstract: The present disclosure relates to a memory cell (1) and to a method of erasing the memory cell (1). The memory cell comprises a doped well (100) of a first conductivity type and a transistor (T). Transistor (T) comprises a doped first region (106) of a second conductivity type opposite to the first conductivity type, the first doped region extending in the doped well (100); a buried doped channel (118) of the second conductivity type extending in the doped well (100); and a gate stack (108) resting on the doped well (100), above the buried doped channel (118). The gate stack (108) comprises a first layer (110) adapted to trap charges, a second insulating layer (112) resting on the first layer and a third conductive layer (114) resting on the second layer.

Abstract: An integrated circuit includes a semiconductor substrate and at least one memory cell provided with a vertical gate selection transistor buried in the substrate and a floating gate state transistor. The floating gate state transistor covers a first active region and a second active region of the substrate delimited by lateral isolation regions. The memory cell includes a lateral isolation region thickness (in breadth) dimension between a sidewall of the vertical gate of the buried transistor and the second active region.

Abstract: The non-volatile memory device includes memory cells including a control gate vertically buried in a semiconductor substrate doped with a first type of dopant and a dielectric interface able to trap electrical charges covering sides of the control gate facing the semiconductor substrate. The device furthermore includes a vertical implanted region of a second type of dopant opposite to the first type located along the sides of the control gate in the semiconductor substrate.

Abstract: In an embodiment a memory cell includes a first doped well of a first conductivity type embedded in a second doped well of a second conductivity type, the second conductivity type being opposite to the first conductivity type, a third doped well of the second conductivity type embedded in a fourth doped well of the first conductivity type, a first wall in contact with the second and fourth doped wells, the first wall including a conductive or semiconductor core and an insulating liner, the insulating liner extending between the conductive or semiconductor core and the second and fourth doped wells, and a stack of layers comprising a first insulating layer, a first semiconductor layer, a second insulating layer and a second semiconductor layer, the first insulating layer being in contact with the second and fourth doped wells.

Abstract: In an embodiment a memory cell includes a first doped well of a first conductivity type in contact with a second doped well of a second conductivity type, the second conductivity type being opposite to the first conductivity type, a third doped well of the second conductivity type in contact with a fourth doped well of the first conductivity type, a first wall in contact with the second and fourth wells, the first wall including a conductive or semiconductor core and an insulating sheath, a stack of layers including a first insulating layer, a first semiconductor layer, a second insulating layer and a second semiconductor layer at least partially covering the second and fourth wells and a third semiconductor layer located below the second and fourth wells and the first wall.

Abstract: In an embodiment a memory cell includes a first doped well of a first conductivity type in contact with a second doped well of a second conductivity type, the second conductivity type being opposite to the first conductivity type, a third doped well of the second conductivity type in contact with a fourth doped well of the first conductivity type, a first wall in contact with the second and fourth wells, the first wall including a conductive or semiconductor core and an insulating sheath, a stack of layers including a first insulating layer, a first semiconductor layer, a second insulating layer and a second semiconductor layer at least partially covering the second and fourth wells and a third semiconductor layer located below the second and fourth wells and the first wall.