Patents by Inventor Franck Sala
Franck Sala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230195469Abstract: Techniques and mechanisms for a processor to determine an execution of instructions based on a prediction of a taken branch. In an embodiment, a first prediction unit generates each of multiple branch predictions in one cycle of successive branch prediction cycles. An indication of the branch predictions is provided to an execution pipeline, which prepares to execute an instruction based on the indication. Where a first one of the branch predictions is determined to be of a low confidence type, said first branch prediction is further indicated to a second prediction unit, which performs a second branch prediction based on the same branch instruction for which the first branch prediction was made. In another embodiment, the second prediction unit signals that a state of the execution pipeline is to be cleared, based on a determination that the first and second branch predictions are inconsistent with each other.Type: ApplicationFiled: December 21, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Sumeet Bandishte, Jayesh Gaur, Franck Sala, Alexey Yurievich Sivtsov, Jared Warner Stark, IV, Lihu Rappoport, Sreenivas Subramoney
-
Patent number: 11656971Abstract: A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state.Type: GrantFiled: January 24, 2022Date of Patent: May 23, 2023Assignee: Intel CorporationInventors: Adarsh Chauhan, Jayesh Gaur, Franck Sala, Lihu Rappoport, Zeev Sperber, Adi Yoaz, Sreenivas Subramoney
-
Patent number: 11645078Abstract: Systems, methods, and apparatuses relating to hardware for auto-predication of critical branches. In one embodiment, a processor core includes a decoder to decode instructions into decoded instructions, an execution unit to execute the decoded instructions, a branch predictor circuit to predict a future outcome of a branch instruction, and a branch predication manager circuit to disable use of the predicted future outcome for a conditional critical branch comprising the branch instruction.Type: GrantFiled: December 28, 2019Date of Patent: May 9, 2023Assignee: Intel CorporationInventors: Adarsh Chauhan, Franck Sala, Jayesh Gaur, Zeev Sperber, Lihu Rappoport, Adi Yoaz, Sreenivas Subramoney
-
Publication number: 20220206925Abstract: A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state.Type: ApplicationFiled: January 24, 2022Publication date: June 30, 2022Inventors: Adarsh Chauhan, Jayesh Gaur, Franck Sala, Lihu Rappoport, Zeev Sperber, Adi Yoaz, Sreenivas Subramoney
-
Patent number: 11256599Abstract: A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state.Type: GrantFiled: December 21, 2020Date of Patent: February 22, 2022Assignee: Intel CorporationInventors: Adarsh Chauhan, Jayesh Gaur, Franck Sala, Lihu Rappoport, Zeev Sperber, Adi Yoaz, Sreenivas Subramoney
-
Publication number: 20210200550Abstract: Disclosed embodiments relate to systems and methods structured to predict a loop exit. In one example, a processor includes a branch prediction unit to determine a loop exit predictor start corresponding to a finite consistent loop, and an instruction decoder queue to: receive an iteration of the finite consistent loop corresponding to a loop exit predictor and an iteration count, replay one or more instructions of the iteration based on the iteration count, and switch to post-loop instructions responsive to a determination that a number of iterations of the finite consistent loop is equal to the iteration count.Type: ApplicationFiled: December 28, 2019Publication date: July 1, 2021Inventors: Alexey Yurievich SIVTSOV, Franck SALA, Jared Warner STARK, IV, Lihu RAPPOPORT
-
Publication number: 20210200538Abstract: Disclosed embodiments relate to systems and methods to dually write micro-ops to a micro-op queue. A processor includes a micro-op cache communicatively coupled, via a first write port, to a micro-op queue, and a legacy fetch and decode pipeline communicatively coupled, via a second write port, to the micro-op queue, the processor to determine whether the micro-op cache stores a thread, the thread comprising a micro-op to be written to the micro-op queue, determine whether the legacy fetch and decode pipeline stores the thread if the micro-op cache does not store the thread, and write, via the micro-op queue, the micro-op from the thread to the micro-op queue responsive to the determination of whether the micro-op cache or the legacy fetch and decode pipeline stores the thread.Type: ApplicationFiled: December 28, 2019Publication date: July 1, 2021Inventors: Franck SALA, Lihu RAPPOPORT
-
Publication number: 20210109839Abstract: A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state.Type: ApplicationFiled: December 21, 2020Publication date: April 15, 2021Inventors: Adarsh Chauhan, Jayesh Gaur, Franck Sala, Lihu Rappoport, Zeev Sperber, Adi Yoaz, Sreenivas Subramoney
-
Patent number: 10915421Abstract: A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state.Type: GrantFiled: September 19, 2019Date of Patent: February 9, 2021Assignee: Intel CorporationInventors: Adarsh Chauhan, Jayesh Gaur, Franck Sala, Lihu Rappoport, Zeev Sperber, Adi Yoaz, Sreenivas Subramoney
-
Publication number: 20210019149Abstract: Systems, methods, and apparatuses relating to hardware for auto-predication of critical branches. In one embodiment, a processor core includes a decoder to decode instructions into decoded instructions, an execution unit to execute the decoded instructions, a branch predictor circuit to predict a future outcome of a branch instruction, and a branch predication manager circuit to disable use of the predicted future outcome for a conditional critical branch comprising the branch instruction.Type: ApplicationFiled: December 28, 2019Publication date: January 21, 2021Inventors: ADARSH CHAUHAN, Franck SALA, Jayesh GAUR, Zeev SPERBER, Lihu RAPPOPORT, Adi YOAZ, Sreenivas SUBRAMONEY
-
Patent number: 10579535Abstract: A processor includes a processor core and a micro-op cache communicably coupled to the processor core. The micro-op cache includes a micro-op tag array, wherein tag array entries in the micro-op tag array are indexed according to set and way of set-associative cache, and a micro-op data array to store multiple micro-ops. The data array entries in the micro-op data array are indexed according to bank number of a plurality of cache banks and to a set within one cache bank of the plurality of cache banks.Type: GrantFiled: December 15, 2017Date of Patent: March 3, 2020Assignee: Intel CorporationInventors: Lihu Rappoport, Jared Warner Stark, IV, Franck Sala, Michael Tal, Gil Shmueli, Adrian Flesler
-
Publication number: 20190213131Abstract: Systems and methods for stream cache memory retrieval include applying a stream cache to predict a sequence of instructions and data across multiple branches. Similar to a conventional computing cache, the stream cache stores and provides data or instructions more quickly than provided by slower data storage media, such as an instruction cache. The stream cache described herein provides the ability to predict instructions and data requests across multiple branches per cycle, and in particular across multiple taken branches per cycle. This stream cache increases instruction supply bandwidth while reducing overall power consumption by saving cycles of the branch predictor structures.Type: ApplicationFiled: January 11, 2018Publication date: July 11, 2019Inventors: Ariel Sabba, Shani Rehana, Michael Tal, Suzan Baransi, Lihu Rappoport, Jared Warner Stark, Franck Sala
-
Publication number: 20190188142Abstract: A processor includes a processor core and a micro-op cache communicably coupled to the processor core. The micro-op cache includes a micro-op tag array, wherein tag array entries in the micro-op tag array are indexed according to set and way of set-associative cache, and a micro-op data array to store multiple micro-ops. The data array entries in the micro-op data array are indexed according to bank number of a plurality of cache banks and to a set within one cache bank of the plurality of cache banks.Type: ApplicationFiled: December 15, 2017Publication date: June 20, 2019Inventors: Lihu RAPPOPORT, Jared Warner Stark iv, Franck Sala, Michael Tal, Gil Shmueli, Adrian Flesler
-
Patent number: 9552169Abstract: A method and apparatus are described for efficient memory renaming prediction using virtual registers. For example, one embodiment of an apparatus comprises: a memory execution unit (MEU) to perform store and load operations to store data to memory and load data from memory, respectively; a plurality of memory rename (MRN) registers assigned to store and load operations, each MRN register to store data associated with a store operation so that the data is available for a subsequent load operation; and at least one MRN predictor comprising a data structure to allocate virtual memory rename (VMRN) registers to each of the MRN registers, the MRN predictor to query the data structure in response to a load and/or store operation using a value identifying the MRN register assigned to the load and/or store operation, respectively, to determine a current VMRN register associated with the load and/or store operation.Type: GrantFiled: May 7, 2015Date of Patent: January 24, 2017Assignee: Intel CorporationInventors: Lihu Rappoport, Jared W. Stark, Kamil Garifullin, Franck Sala, Pavel I. Kryukov, Stanislav Shwartsman
-
Publication number: 20160328172Abstract: A method and apparatus are described for efficient memory renaming prediction using virtual registers. For example, one embodiment of an apparatus comprises: a memory execution unit (MEU) to perform store and load operations to store data to memory and load data from memory, respectively; a plurality of memory rename (MRN) registers assigned to store and load operations, each MRN register to store data associated with a store operation so that the data is available for a subsequent load operation; and at least one MRN predictor comprising a data structure to allocate virtual memory rename (VMRN) registers to each of the MRN registers, the MRN predictor to query the data structure in response to a load and/or store operation using a value identifying the MRN register assigned to the load and/or store operation, respectively, to determine a current VMRN register associated with the load and/or store operation.Type: ApplicationFiled: May 7, 2015Publication date: November 10, 2016Inventors: LIHU RAPPOPORT, JARED W. STARK, KAMIL GARIFULLIN, FRANCK SALA, PAVEL I. KRYUKOV, STANISLAV SHWARTSMAN
-
Patent number: 9459871Abstract: A method, system, and computer program product for identifying loop information corresponding to a plurality of loop instructions. The loop instructions are stored into a queue. The loop instructions are replayed from the queue for execution. Loop iteration is counted based on the identified loop information. A determination is made of whether the last iteration of the loop is done. If the last iteration is not done, then embodiments continue replaying the loop instructions, until the last iteration is done.Type: GrantFiled: December 31, 2012Date of Patent: October 4, 2016Assignee: Intel CorporationInventors: Masha Lipshits, Lihu Rappaport, Shantanu Gupta, Franck Sala, Naveen Kumar, Allan D. Knies
-
Patent number: 8782374Abstract: Methods and apparatus for inclusion of TLB (translation look-aside buffer) in processor micro-op caches are disclosed. Some embodiments for inclusion of TLB entries have micro-op cache inclusion fields, which are set responsive to accessing the TLB entry. Inclusion logic may the flush the micro-op cache or portions of the micro-op cache and clear corresponding inclusion fields responsive to a replacement or invalidation of a TLB entry whenever its associated inclusion field had been set. Front-end processor state may also be cleared and instructions refetched when replacement resulted from a TLB miss.Type: GrantFiled: December 2, 2008Date of Patent: July 15, 2014Assignee: Intel CorporationInventors: Lihu Rappoport, Chen Koren, Franck Sala, Oded Lempel, Ido Ouziel, Ron Gabor, Gregory Pribush, Lior Libis
-
Publication number: 20140189331Abstract: An method may include identifying loop information corresponding to a plurality of loop instructions. The loop instructions are stored into a queue. The loop instructions are replayed from the queue for execution. Loop iteration is counted based on the identified loop information. A determination of whether the last iteration of the loop is done. If the last iteration is not done, then continue replaying the loop instructions, until the last iteration is done.Type: ApplicationFiled: December 31, 2012Publication date: July 3, 2014Inventors: Maria Lipshits, Lihu Rappoport, Shantanu Gupta, Franck Sala, Naveen Kumar, Allan D. Knies
-
Publication number: 20140143526Abstract: In one embodiment, a processor includes at least one execution unit. The processor also includes prediction gating logic coupled to the at least one execution unit. The prediction gating logic may be to, in response to a first prediction that a first branch is taken, obtain a distance value to a second branch using a target array, and gate a branch prediction unit for a number of instruction blocks equal to the distance value to the second branch. Other embodiments are described and claimed.Type: ApplicationFiled: November 20, 2012Publication date: May 22, 2014Inventors: Polychronis Xekalakis, Pedro Marcuello, Fernando Latorre, Franck Sala, Gershon Rubinstein
-
Patent number: 8433850Abstract: Methods and apparatus for instruction restarts and inclusion in processor micro-op caches are disclosed. Embodiments of micro-op caches have way storage fields to record the instruction-cache ways storing corresponding macroinstructions. Instruction-cache in-use indications associated with the instruction-cache lines storing the instructions are updated upon micro-op cache hits. In-use indications can be located using the recorded instruction-cache ways in micro-op cache lines. Victim-cache deallocation micro-ops are enqueued in a micro-op queue after micro-op cache miss synchronizations, responsive to evictions from the instruction-cache into a victim-cache. Inclusion logic also locates and evicts micro-op cache lines corresponding to the recorded instruction-cache ways, responsive to evictions from the instruction-cache.Type: GrantFiled: December 2, 2008Date of Patent: April 30, 2013Assignee: Intel CorporationInventors: Lihu Rappoport, Chen Koren, Franck Sala, Ilhyun Kim, Lior Libis, Ron Gabor, Oded Lempel