Patents by Inventor Franco Maggioni

Franco Maggioni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6167045
    Abstract: Information providers act as sources of information consisting of a plurality of variable length messages and issue control packets, enabling/disabling packets and data packets. Each data receiver has a unique address as a permanent attribute. The enabling/disabling packets selectively enable or disable a specific data receiver or a specific group of data receivers. Therefore to avoid that the loss of the enabling/disabling packet leads to the loss of the corresponding whole set of packets, each data receiver stores data packets for later use in the re-establishment of the entire set of transmission packets. However, only data packets provided by any FRIEND information provider (i.e. information provider from which the data receiver is authorized to receive information on a selective basis) are managed by the data receiver.
    Type: Grant
    Filed: December 8, 1997
    Date of Patent: December 26, 2000
    Assignee: International Business Machines Corporation
    Inventors: Tullio Pirovano, Franco Maggioni
  • Patent number: 4968645
    Abstract: A monolithic integrated circuit of either the MOS or CMOS type comprises an intermediate layer of polycrystalline silicon, a layer of a silicide of a refractory metal overlying said polycrystalline silicon layer, and regions of preset area and preset paths formed in the polycrystalline silicon layer and the silicide layer; the preset area regions and preset paths forming respectively high resistivity resistances and low resistivity interconnection lines for an intermediate connection level.
    Type: Grant
    Filed: December 15, 1988
    Date of Patent: November 6, 1990
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Livio Baldi, Paolo G. Cappelletti, Franco Maggioni
  • Patent number: 4780431
    Abstract: The process provides for obtaining in the areas intended for the formation of the transistors windows in the intermediate oxide layer between the two silicon layers and, before final etching of the two silicon layers and the intermediate oxide, application of a mask formed in such a manner as to superimpose on the second silicon layer in the transistor areas coverings wider than the corresponding windows of the intermediate oxide layer.
    Type: Grant
    Filed: July 2, 1987
    Date of Patent: October 25, 1988
    Assignee: SGS Microellettronica S.p.A.
    Inventors: Franco Maggioni, Carlo Riva