Abstract: A storage cell of a nonvolatile electrically alterable MOS memory (EAROM) comprises a p-type silicon substrate with n-doped drain and source areas interlinked by an n-channel which is partly overlain by a floating gate extending over part of the drain area. An accessible gate overlaps the floating gate and has an extension overlying a gap between the latter gate and the source area to act as a common control electrode for two series IGFETs defined by the source and gate areas, namely a main or storage transistor and an ancillary or switching transistor. The capacitance of the floating gate relative to the drain area accounts for about half the overall capacitance of that gate relative to the entire semiconductor structure.