Abstract: A driver circuit, in accordance with one example, includes a controllable current source operably coupled to the load and configured to sink or source a first current in accordance with a control signal. A controllable switch is responsive to an input signal, operably coupled to the current source, and configured to take over, or not, the first current in accordance with an input signal. The first current is directed as a load current through the load when the controllable switch is driven into a blocking state. The first current is directed through the controllable switch when the controllable switch is driven into a conducting state thus bypassing the load. An input signal includes a first series of pulses defining the desired load current waveform in accordance with a desired modulation scheme.

Abstract: A method controls a power MOS transistor having a control terminal and a load path, the load path connected in series with a load between voltage supply terminals, wherein a power supply voltage between the voltage supply terminals imposes a load voltage across the load and a load path voltage across the load path of the power MOS transistor. The method includes generating a control current for the control terminal during a switching process when the power MOS transistor changes switching states. The control current is dependent on the power supply voltage and on at least one of the group consisting of the load path voltage and the load voltage.

Abstract: Embodiments of the invention are related to a power transistor and a method for controlling a power transistor. In one embodiment a power transistor comprises a power semiconductor body with a plurality of power transistor cells each having a control electrode and a current path. The power transistor furthermore comprises a temperature sensor formed by at least one transistor cell in the power semiconductor body whose control electrode is coupled to one electrode of the current path forming a reversed biased pn-junction.

Abstract: Embodiments of the invention are related to a power transistor and a method for controlling a power transistor. In one embodiment a power transistor comprises a power semiconductor body with a plurality of power transistor cells each having a control electrode and a current path. The power transistor furthermore comprises a temperature sensor formed by at least one transistor cell in the power semiconductor body whose control electrode is coupled to one electrode of the current path forming a reversed biased pn-junction.

Abstract: A circuit includes a MOS transistor having a control electrode and a control capacitance, and including a control circuit for the MOS transistor. The control circuit includes an input to supply a control signal and an output to supply a drive signal, the output being connected to the control electrode of the MOS transistor. A calibration circuit is connected to the control electrode of the MOS transistor, and generates a calibration signal dependent on the capacitance value of the control capacitance. A drive circuit generates the drive signal with an amplitude dependent on the calibration signal as determined by the control signal.

Abstract: An interface circuit includes an input terminal, a controlled current sink, a current measurement arrangement, and a logic circuit. The input terminal is configured to receive an input signal. The controlled current sink is operably coupled to the input terminal, and is operable to controllably take up a current from the input terminal according to a transmission signal. The current measurement arrangement is configured to generate a current measurement signal based on the current taken up by the current sink. The logic circuit is operably coupled to receive the current measurement signal and the input signal, and is configured to generate a signal depending on the input signal.

Abstract: A circuit includes a MOS transistor having a control electrode and a control capacitance, and including a control circuit for the MOS transistor. The control circuit includes an input to supply a control signal and an output to supply a drive signal, the output being connected to the control electrode of the MOS transistor. A calibration circuit is connected to the control electrode of the MOS transistor, and generates a calibration signal dependent on the capacitance value of the control capacitance. A drive circuit generates the drive signal with an amplitude dependent on the calibration signal as determined by the control signal.

Abstract: A method controls a power MOS transistor having a control terminal and a load path, the load path connected in series with a load between voltage supply terminals, wherein a power supply voltage between the voltage supply terminals imposes a load voltage across the load and a load path voltage across the load path of the power MOS transistor. The method includes generating a control current for the control terminal during a switching process when the power MOS transistor changes switching states. The control current is dependent on the power supply voltage and on at least one of the group consisting of the load path voltage and the load voltage.

Abstract: An interface circuit includes an input terminal, a controlled current sink, a current measurement arrangement, and a logic circuit. The input terminal is configured to receive an input signal. The controlled current sink is operably coupled to the input terminal, and is operable to controllably take up a current from the input terminal according to a transmission signal. The current measurement arrangement is configured to generate a current measurement signal based on the current taken up by the current sink. The logic circuit is operably coupled to receive the current measurement signal and the input signal, and is configured to generate a signal depending on the input signal.