Abstract: A device and associated methods for the storage and retrieval of data elements in a buffer circuit include each data element being transmitted to the buffer circuit through a transmission bus and a bus interface. A data element is stored in a memory when a first register is not empty. Additionally, when the first register is not empty, a data element is also stored in an additional register directly accessible by a decoding interface. The time of access to the data elements in the buffer circuit may be reduced.

Abstract: A microprocessor circuit having an external memory interface includes a transmission element for the transmission of binary data packets between the microprocessor and the interface. The interface includes a buffer with a determined capacity for storing the transmitted data elements. The circuit also includes a controller capable of computing the capacity of the buffer that is available or unavailable owing to the storage of the data elements and capable of reporting the status of availability of the buffer to receive an additional packet. A method is also provided for the control of the interface of such a circuit. The interface comprises a decoder for decoding format data of a packet. The format data of a packet being contained in the data packet and each format data decoding operation being given to the controller in order to optimize the use of the storage capacity of the buffer and the transmission between the microprocessor and the external memory.