Abstract: An electronic control cell for at least one organic light-emitting diode (OLED) of a pixel or segment of an active matrix display, the cell including at least one control circuit (6,61,62) with a control input and operating relative to a control signal arriving at a control line (5,5?) and enabling to turn the OLED(s) on, one capacitive storage circuit of the control signal with a capacitor C connected to the control line, one selection circuit (4,41,42) operating relative to a selection signal Vsel on a selection line (3,3?) and enabling electrical connection or insulation of the capacitive storage circuit with/from a control voltage Vcom (2) relative to the selection signal. The storage is temporary by discharging the capacitor through a resistor Rf parallel to the capacitor. Operating methods and a display unit are also disclosed.

Abstract: This invention relates to an optical interconnection system in a microelectronic circuit made on an SOI substrate (30), in other words a substrate with a silicon film (13, 33, 53) supported by a layer of electrically insulating material (32), the microelectronic circuit comprising at least one function block to be connected made in the silicon film. The system comprises at least one optical microguide composed of a strip (40) delimited in the silicon film by lateral confinement areas (41, 42) to connect the function block.

Abstract: A dynamic logic array circuit can operate in two clock phases. It includes two matrices (1, 2) comprising dynamic logical gates, which require a precharging phase that precedes a functional phase. The array also includes memorizing means (7), the inputs of which are connected to the outputs of the first matrix (1) via first controlled isolating means (8), the outputs (MEO) of the memorizing means being connected to the inputs of the second matrix (2) via second controlled isolating means (9), the first isolating means (8) being controlled for authorizing the transfer of the signals emitted by the first matrix (1) to the memorizing means (7) during the precharging phase (PHO) of the second matrix (2) and the second isolating means (9) being controlled for authorizing the transfer of the data contained in the memorizing means (7) to the second matrix (2) during the precharging phase (PH1) of the first matrix (1). The invention is particularly applicable to CMOS technology.

Abstract: A device for coupling several data processing units to a central memory, the processing units being each provided with means for exchanging data with peripheral devices and with computing means, the device includes management means for controlling the sequential execution of orders issued from the memory, according to a hierarchical classification of the lists of tasks for the exchange processes and the computing process and further includes devices for commutation upon control of decoding means of a signal produced by the processing units, in accordance with the value of a binary digit associated to a task of a fresh list of actuatable tasks established in a non-hierarchical system.

Abstract: Microprogrammed computing device comprising a data processing system, a central memory operatively connected thereto, means for exchanging data with peripheral devices, a system for controlling the execution of orders issued from the memory, a system for hierarchically classifying the tasks in a list and making the processing system available for the task having the first priority and a system for managing said list, means for testing the availability of said peripheral devices and means for adapting the processing system to each new task to which the first priority is given, whereby several computing and data exchange processes may be performed by the same device.