Abstract: A device includes a first set of storage elements, a second set of storage elements, and a bias circuit configured to generate a test bias signal to bias the first set of storage elements and the second set of storage elements. The device further includes a sensor circuit configured to receive a first signal from at least a first storage element of the first set of storage elements in response to the test bias signal and to receive a second signal from at least a second storage element of the second set of storage elements in response to the test bias signal. The sensor circuit is further configured to generate a third signal having a delay characteristic indicating a wear difference between the first storage element and the second storage element.

Abstract: A random access memory circuit comprises a plurality of memory cells and at least one decoder coupled to the memory cells, the decoder being configurable for receiving an input address and for accessing one or more of the memory cells in response thereto. The random access memory circuit further comprises a plurality of sense amplifiers operatively coupled to the memory cells, the sense amplifiers being configurable for determining a logical state of one or more of the memory cells. A controller coupled to at least a portion of the sense amplifiers is configurable for selectively operating in at least one of a first mode and a second mode. In the first mode of operation, the controller enables one of the sense amplifiers corresponding to the input address and disables the sense amplifiers not corresponding to the input address. In the second mode of operation, the controller enables substantially all of the sense amplifiers.