Patents by Inventor Francois Hebert

Francois Hebert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • HIGH-EFFICIENCY POWER CONVERTERS WITH INTEGRATED CAPACITORS
    Publication number: 20120098090
    Abstract: A power converter device comprises a substrate, a power die mounted on the substrate, and a capacitor die mounted over the power die in a stacked configuration. The capacitor die is electrically coupled to the power die. A packaging material encapsulates the power die and the capacitor die. An integrated circuit die can also be mounted to the substrate and electrically coupled to the power die to receive power signals from the power die, with the packaging material also encapsulating the integrated circuit die.
    Type: Application
    Filed: March 23, 2011
    Publication date: April 26, 2012
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Francois Hebert, Shea Petricek, Nikhil Kelkar
  • Multi-die DC-DC buck power converter with efficient packaging
    Patent number: 8148817
    Abstract: A DC-DC buck converter in multi-die package is proposed having an output inductor, a low-side Schottky diode and a high-side vertical MOSFET controlled by a power regulating controller (PRC). The multi-die package includes a first die pad with the Schottky diode placed there on side by side with the vertical MOSFET. The PRC die is attached atop the first die pad via an insulating die bond. Alternatively, the first die pad is grounded. The vertical MOSFET is a top drain N-channel FET, the substrate of Schottky diode die is its anode. The Schottky diode and the vertical MOSFET are stacked atop the first die pad. The PRC is attached atop the first die pad via a conductive die bond. The Schottky diode die can be supplied in a flip-chip configuration with cathode being its substrate. Alternatively, the Schottky diode is supplied with anode being its substrate without the flip-chip configuration.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: April 3, 2012
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: François Hébert, Allen Chang
  • Copper bonding method
    Patent number: 8148256
    Abstract: A copper bonding compatible bond pad structure and associated method is disclosed. The device bond pad structure includes a buffering structure formed of regions of interconnect metal and regions of non-conductive passivation material, the buffering structure providing buffering of underlying layers and structures of the device.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: April 3, 2012
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: François Hébert, Anup Bhalla
  • COPPER BONDING COMPATIBLE BOND PAD STRUCTURE AND METHOD
    Publication number: 20120064711
    Abstract: A copper bonding compatible bond pad structure and associated method is disclosed. The device bond pad structure includes a buffering structure formed of regions of interconnect metal and regions of non-conductive passivation material, the buffering structure providing buffering of underlying layers and structures of the device.
    Type: Application
    Filed: November 17, 2011
    Publication date: March 15, 2012
    Inventors: François Hébert, Arup Bhalia
  • Compact Semiconductor Package with Integrated Bypass Capacitor
    Publication number: 20120032244
    Abstract: A top-side cooled compact semiconductor package with integrated bypass capacitor is disclosed. The top-side cooled compact semiconductor package includes a circuit substrate with terminal leads, numerous semiconductor dies bonded atop the circuit substrate, numerous elevation-adaptive interconnection plates for bonding and interconnecting top contact areas of the semiconductor dies with the circuit substrate, a first member of the elevation-adaptive interconnection plates has a first flat-top area and a second member of the elevation-adaptive interconnection plates has a second flat-top area in level with the first flat-top area, a bypass capacitor, having two capacitor terminals located at its ends, stacked atop the two interconnection plate members while being bonded thereto via the first flat-top area and the second flat-top area for a reduced interconnection parasitic impedance.
    Type: Application
    Filed: October 14, 2011
    Publication date: February 9, 2012
    Inventors: François Hébert, Kai Liu
  • High power and high temperature semiconductor power devices protected by non-uniform ballasted sources
    Patent number: 8110472
    Abstract: A semiconductor power device is formed on a semiconductor substrate. The semiconductor power device includes a plurality of transistor cells distributed over different areas having varying amount of ballasting resistances depending on a local thermal dissipation in each of the different areas. An exemplary embodiment has the transistor cells with a lower ballasting resistance formed near a peripheral area and the transistor cells having a higher ballasting resistance are formed near a bond pad area. Another exemplary embodiment comprises cells with a highest ballasting resistance formed in an area around a wire-bonding pad, the transistor cells having a lower resistance are formed underneath the wire-bonding pad connected to bonding wires for dissipating heat and the transistor cells having a lowest ballasting resistance are formed in an areas away from the bonding pad.
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: February 7, 2012
    Assignee: Alpha and Omega Semiconductor Ltd
    Inventors: François Hébert, Anup Bhalla
  • Inverted-trench grounded-source FET structure using conductive substrates, with highly doped substrates
    Publication number: 20120028426
    Abstract: This invention discloses an inverted field-effect-transistor (iT-FET) semiconductor device that includes a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate. The semiconductor power device further comprises a trench-sidewall gate placed on sidewalls at a lower portion of a vertical trench surrounded by a body region encompassing a source region with a low resistivity body-source structure connected to a bottom source electrode and a drain link region disposed on top of said body regions thus constituting a drift region. The drift region is operated with a floating potential said iT-FET device achieving a self-termination.
    Type: Application
    Filed: October 4, 2011
    Publication date: February 2, 2012
    Inventor: François Hébert
  • Inverted-trench grounded-source FET structure with trenched source body short electrode
    Publication number: 20120025301
    Abstract: This invention discloses bottom-source lateral diffusion MOS (BS-LDMOS) device. The device has a source region disposed laterally opposite a drain region near a top surface of a semiconductor substrate supporting a gate thereon between the source region and a drain region. The BS-LDMOS device further has a combined sinker-channel region disposed at a depth in the semiconductor substrate entirely below a body region disposed adjacent to the source region near the top surface wherein the combined sinker-channel region functioning as a buried source-body contact for electrically connecting the body region and the source region to a bottom of the substrate functioning as a source electrode. A drift region is disposed near the top surface under the gate and at a distance away from the source region and extending to and encompassing the drain region.
    Type: Application
    Filed: August 25, 2011
    Publication date: February 2, 2012
    Inventors: Sik K. Lui, François Hébert, Anup Bhalla
  • Device structure and manufacturing method using HDP deposited using deposited source-body implant block
    Publication number: 20120018793
    Abstract: This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.
    Type: Application
    Filed: October 4, 2011
    Publication date: January 26, 2012
    Inventors: Anup Bhalla, François Hébert, Sung-Shan Tai, Sik K. Lui
  • SCHOTTKY DIODE WITH COMBINED FIELD PLATE AND GUARD RING
    Publication number: 20120007097
    Abstract: A Schottky diode comprising a merged guard ring and field plate defining a Schottky contact region is provided. A Schottky metal is formed over at least partially over the Schottky contact region and at least partially over the merged guard ring and field plate.
    Type: Application
    Filed: November 11, 2010
    Publication date: January 12, 2012
    Applicant: INTERSIL AMERICAS INC.
    Inventor: Francois Hebert
  • HIGH POWER AND HIGH TEMPERATURE SEMICONDUCTOR POWER DEVICES PROTECTED BY NON-UNIFORM BALLASTED SOURCES
    Publication number: 20110306175
    Abstract: A semiconductor power device is formed on a semiconductor substrate. The semiconductor power device includes a plurality of transistor cells distributed over different areas having varying amount of ballasting resistances depending on a local thermal dissipation in each of the different areas. An exemplary embodiment has the transistor cells with a lower ballasting resistance formed near a peripheral area and the transistor cells having a higher ballasting resistance are formed near a bond pad area. Another exemplary embodiment comprises cells with a highest ballasting resistance formed in an area around a wire-bonding pad, the transistor cells having a lower resistance are formed underneath the wire-bonding pad connected to bonding wires for dissipating heat and the transistor cells having a lowest ballasting resistance are formed in an areas away from the bonding pad.
    Type: Application
    Filed: August 23, 2011
    Publication date: December 15, 2011
    Inventors: Francois Hébert, Anup Bhalla
  • Bottom anode schottky diode structure and method
    Publication number: 20110287616
    Abstract: This invention discloses a bottom-anode Schottky (BAS) diode that includes an anode electrode disposed on a bottom surface of a semiconductor substrate. The bottom-anode Schottky diode further includes a sinker dopant region disposed at a depth in the semiconductor substrate extending substantially to the anode electrode disposed on the bottom surface of the semiconductor and the sinker dopant region covered by a buried Schottky barrier metal functioning as a Schottky anode.
    Type: Application
    Filed: June 30, 2011
    Publication date: November 24, 2011
    Inventor: François Hébert
  • Compact semiconductor package with integrated bypass capacitor and method
    Patent number: 8062932
    Abstract: A top-side cooled compact semiconductor package with integrated bypass capacitor is disclosed. The top-side cooled compact semiconductor package includes a circuit substrate with terminal leads, numerous semiconductor dies bonded atop the circuit substrate, numerous elevation-adaptive interconnection plates for bonding and interconnecting top contact areas of the semiconductor dies with the circuit substrate, a first member of the elevation-adaptive interconnection plates has a first flat-top area and a second member of the elevation-adaptive interconnection plates has a second flat-top area in level with the first flat-top area, a bypass capacitor, having two capacitor terminals located at its ends, stacked atop the two interconnection plate members while being bonded thereto via the first flat-top area and the second flat-top area for a reduced interconnection parasitic impedance.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: November 22, 2011
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: François Hébert, Kai Liu
  • HIGH-MOBILITY TRENCH MOSFETS
    Publication number: 20110278665
    Abstract: High-mobility vertical trench DMOSFETs and methods for manufacturing are disclosed. A source region, a drain region or a channel region of a high-mobility vertical trench DMOSFET may comprise silicon germanium (SiGe) that increases the mobility of the charge carriers in the channel region. In some embodiments the channel region may be strained to increase channel charge carriers mobility.
    Type: Application
    Filed: July 22, 2011
    Publication date: November 17, 2011
    Applicant: ALPHA & OMEGA SEMICONDUCTOR, LTD
    Inventor: FRANÇOIS HÉBERT
  • Chip scale power converter package having an inductor substrate
    Patent number: 8058960
    Abstract: A chip scale power converter package having an inductor substrate and a power integrated circuit flipped onto the inductor substrate is disclosed. The inductor substrate includes a high resistivity substrate having a planar spiral inductor formed thereon.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: November 15, 2011
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: François Hébert, Ming Sun
  • Lead frame-based discrete power inductor
    Patent number: 8058961
    Abstract: A lead frame-based discrete power inductor is disclosed. The power inductor includes top and bottom lead frames, the leads of which form a coil around a single closed-loop magnetic core. The coil includes interconnections between inner and outer contact sections of the top and bottom lead frames, the magnetic core being sandwiched between the top and bottom lead frames. Ones of the leads of the top and bottom lead frames have a generally non-linear, stepped configuration such that the leads of the top lead frame couple adjacent leads of the bottom lead frame about the magnetic core to form the coil.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: November 15, 2011
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: François Hébert, Tao Feng, Xiaotian Zhang, Jun Lu
  • Planar split-gate high-performance MOSFET structure and manufacturing method
    Patent number: 8053298
    Abstract: This invention discloses an improved semiconductor power device includes a plurality of power transistor cells wherein each cell further includes a planar gate padded by a gate oxide layer disposed on top of a drift layer constituting an upper layer of a semiconductor substrate wherein the planar gate further constituting a split gate including a gap opened in a gate layer whereby the a total surface area of the gate is reduced. The transistor cell further includes a JFET (junction field effect transistor) diffusion region disposed in the drift layer below the gap of the gate layer wherein the JFET diffusion region having a higher dopant concentration than the drift region for reducing a channel resistance of the semiconductor power device.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: November 8, 2011
    Assignee: Alpha & Omega Semiconductor Ltd.
    Inventors: Anup Bhalla, Francois Hebert, Daniel S. Ng
  • Method to manufacture split gate with high density plasma oxide layer as inter-polysilicon insulation layer
    Patent number: 8053315
    Abstract: This invention discloses a method of manufacturing a trenched semiconductor power device with split gate filling a trench opened in a semiconductor substrate wherein the split gate is separated by an inter-poly insulation layer disposed between a top and a bottom gate segments. The method further includes a step of forming the inter-poly layer by applying a RTP process after a HDP oxide deposition process to bring an etch rate of the HDP oxide layer close to an etch rate of a thermal oxide.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: November 8, 2011
    Assignee: Alpha & Omega Semiconductor, LTD
    Inventors: Sung-Shan Tai, Yong-Zhong Hu, François Hébert, Hong Chang, Mengyu Pan, Yingying Lou, Yu Wang
  • Inverted-trench grounded-source FET structure using conductive substrates, with highly doped substrates
    Patent number: 8053834
    Abstract: This invention discloses an inverted field-effect-transistor (iT-FET) semiconductor device that includes a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate. The semiconductor power device further comprises a trench-sidewall gate placed on sidewalls at a lower portion of a vertical trench surrounded by a body region encompassing a source region with a low resistivity body-source structure connected to a bottom source electrode and a drain link region disposed on top of said body regions thus constituting a drift region. The drift region is operated with a floating potential said iT-FET device achieving a self-termination.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: November 8, 2011
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventor: François Hébert
  • GaN BASED POWER DEVICES WITH INTEGRATED PROTECTION DEVICES: STRUCUTRES AND METHODS
    Publication number: 20110260216
    Abstract: Exemplary embodiments provide structures and methods for power devices with integrated clamp structures. The integration of clamp structures can protect the power device, e.g., from electrical overstress (EOS). In one embodiment, active devices can be formed over a substrate, while a clamp structure can be integrated outside the active regions of the power device, for example, under the active regions and/or inside the substrate. Integrating clamp structure outside active regions of power devices can maximize the active area for a given die size and improve robustness of the clamped device since the current will spread in the substrate by this integration.
    Type: Application
    Filed: November 19, 2010
    Publication date: October 27, 2011
    Inventor: Francois Hebert