Abstract: An incoming signal's duty cycle is transformed to a known value by a first programmable duty cycle generator, and the output of the first programmable duty cycle generator is applied to a second programmable duty cycle generator which includes multiple stages which provide multiple duty cycle tap point outpoints, each having a different known value of a precise duty cycle, wherein the leading edges or trailing edges of the multiple duty cycle tap point output signals are phase aligned with respect to each other by voltage controlled delay matching elements which are replicas of the stages of the second duty cycle generator.

Abstract: A precise and programmable duty cycle generator which can produce a user definable duty cycle clock signal with precision. This circuit is comprised of a number of generally known circuit elements such as a digital to analog converter (DAC), low pass filter (LPF) and operational transconductance amplifier (OTA), as well as a unique voltage controlled duty cycle generator (VCDCG). The circuit has the ability to produce a user programmable duty cycle clock signal with precision over a broad range of operational frequencies. The VCDCG circuit is unique and employs a number of stages, each of which has a current starved inverter which is immediately followed by a conventional inverter to allow duty cycle corrections to be either additive or subtractive. The current starved inverters are controlled by a single voltage, which causes the current starved inverter's delay to degrade/improve on only one transition to effect a change in the duty cycle.

Abstract: An incoming signal's duty cycle is transformed to a known value by a first programmable duty cycle generator, and the output of the first programmable duty cycle generator is applied to a second programmable duty cycle generator which includes multiple stages which provide multiple duty cycle tap point outpoints, each having a different known value of a precise duty cycle, wherein the leading edges or trailing edges of the multiple duty cycle tap point output signals are phase aligned with respect to each other by voltage controlled delay matching elements which are replicas of the stages of the second duty cycle generator.

Abstract: A precise and programmable duty cycle generator which can produce a user definable duty cycle clock signal with precision. This circuit is comprised of a number of generally known circuit elements such as a digital to analog converter (DAC), low pass filter (LPF) and operational transconductance amplifier (OTA), as well as a unique voltage controlled duty cycle generator (VCDCG). The circuit has the ability to produce a user programmable duty cycle clock signal with precision over a broad range of operational frequencies. The VCDCG circuit is unique and employs a number of stages, each of which has a current starved inverter which is immediately followed by a conventional inverter to allow duty cycle corrections to be either additive or subtractive. The current starved inverters are controlled by a single voltage, which causes the current starved inverter's delay to degrade/improve on only one transition to effect a change in the duty cycle.

Abstract: A precise programmable duty cycle generator employs multiple duty cycle generators connected in series to provide multiple duty cycle tap point outputs, each with a known and precise value of a duty cycle from a source input signal having any duty cycle. The present invention transforms an incoming signal's duty cycle to a known value by a first programmable duty cycle generator, and then applies the output of the first programmable duty cycle generator to a second programmable duty cycle generator which provides multiple duty cycle tap point outputs, each having a different known value of a precise duty cycle.

Abstract: A precise programmable duty cycle generator employs multiple duty cycle generators connected in series to provide multiple duty cycle tap point outputs, each with a known and precise value of a duty cycle from a source input signal having any duty cycle. The present invention transforms an incoming signal's duty cycle to a known value by a first programmable duty cycle generator, and then applies the output of the first programmable duty cycle generator to a second programmable duty cycle generator which provides multiple duty cycle tap point outputs, each having a different known value of a precise duty cycle.

Abstract: A precise and programmable duty cycle adjuster which can produce a user definable duty cycle clock signal comprises a digital to analog converter (DAC), low pass filter (LPF), operational transconductance amplifier (OTA), and a unique voltage controlled duty cycle generator (VCDCG). The circuit has the ability to produce a user programmable duty cycle clock signal with precision over a broad range of operational frequencies. The VCDCG circuit employs a number of delay stages, each of which has a current starved inverter which is immediately followed by a conventional inverter to allow duty cycle corrections to be either additive or subtractive. For a fixed number of delay stages, the range of duty cycle selection is inversely proportional to the frequency of an input clock signal. This frequency range limitation is alleviated by designing the VCDCG with a multiple number of delay taps in conjunction with multiple tap points which are multiplexed at the output.

Abstract: A VLSI chip is disclosed having reduced power dissipation. This is accomplished by limiting the output voltage swing at the output of off chip driver circuits by utilization of a control circuit to regulate the gate bias voltage of an NFET pull-up transistor coupled to the output of the driver circuit and by feeding back the output of the driver circuit to the control circuit.

Abstract: A content addressable memory in accordance with the present invention includes a number of bistable memory cells having as inputs thereto first and second bit lines and an address line, and a COMPARE circuit connected to each of the memory cells so as to provide the COMPARE function without loading the first and second bit lines and including means for inhibiting current flow when a miscompare occurs.

Abstract: Described is a circuit arrangement which controls the range of input voltages at which the output of a CMOS inverter switches. The circuit arrangement includes a plurality of FET devices disposed in parallel with one of the CMOS inverter devices. The FET devices are selectively switched to adjust the (W/L) ratio of said one of the CMOS inverter devices. Therefore, as the switching threshold of the inverter changes due to tempeature, process variations, etc., the (W/L) ratio of the said one of the CMOS inverter devices is adjusted to compensate for the changes.

Abstract: An improved dual media transceiver for terminating an electrical transmission line wherein the transmission line may be a coaxial cable or a shielded twisted pair line. A length of shielded twisted pair line is provided for interconnection. A connector for receiving the transmission line is also provided, adapted to connect the twisted pair wires of the transmission line to a first end of the twisted pair wires of the interconnection line when the transmission line is twisted pair line, and, when the transmission line is coaxial cable, adapted to connect a center conductor of the transmission line to one of the twisted pair wires, at the first end, and the shield of the transmission line to the shield of the interconnection line at the first end. A center tap termination network is connected to the second end of the interconnection line, having a center tap port connected to the shield of the line. The twisted pair wires of the line are connected to the non-center tap ports of the termination network.