Patents by Inventor Francois Ibrahim Atallah
Francois Ibrahim Atallah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160247559Abstract: Read-assist circuits for memory bit cells employing a P-type Field-Effect Transistor (PFET) read port(s) are disclosed. Related memory systems and methods are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type FET (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide memory bit cells having PFET read ports, as opposed to NFET read ports, to increase memory read times to the memory bit cells, and thus improve memory read performance. To mitigate or avoid a read disturb condition that could otherwise occur when reading the memory bit cell, read-assist circuits are provided for memory bit cells having PFET read ports.Type: ApplicationFiled: September 23, 2015Publication date: August 25, 2016Inventors: Francois Ibrahim Atallah, Keith Alan Bowman, David Joseph Winston Hansquine, Jihoon Jeong, Hoan Huu Nguyen
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Patent number: 9413344Abstract: Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems, are disclosed. The adaptive clock distribution system includes a tunable-length delay circuit to delay distribution of a clock signal provided to a clocked circuit, to prevent timing margin degradation of the clocked circuit after a voltage droop occurs in a power supply supplying power to the clocked circuit. The adaptive clock distribution system also includes a dynamic variation monitor to reduce frequency of the delayed clock signal provided to the clocked circuit in response to the voltage droop in the power supply, so that the clocked circuit is not clocked beyond its performance limits during a voltage droop. An automatic calibration circuit is provided in the adaptive clock distribution system to calibrate the dynamic variation monitor during operation based on operational conditions and environmental conditions of the clocked circuit.Type: GrantFiled: March 25, 2015Date of Patent: August 9, 2016Assignee: QUALCOMM IncorporatedInventors: Keith Alan Bowman, Jeffrey Todd Bridges, Sarthak Raina, Yeshwant Nagaraj Kolla, Jihoon Jeong, Francois Ibrahim Atallah, William Robert Flederbach, Jeffrey Herbert Fischer
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Patent number: 9330785Abstract: In a static random access memory (SRAM), such as an SRAM cache in a processor or system-on-a-chip (SoC) device, an aging sensor is provided for testing degradation of SRAM cells comprising p-channel metal oxide semiconductor (PMOS) transistors. The minimum power supply voltage VDDMIN for the SRAM may be dynamically scaled up as the SRAM ages by performing read tests with and without the wordline overdrive voltage VWLOD.Type: GrantFiled: April 29, 2015Date of Patent: May 3, 2016Assignee: QUALCOMM IncorporatedInventors: Venkatasubramanian Narayanan, Keith Alan Bowman, Alex Dongkyu Park, Francois Ibrahim Atallah
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Publication number: 20160091918Abstract: Systems and methods are directed to a configurable last level driver coupled to a inductor-capacitor (LC) tank or resonant clock, for improving energy efficiency of the resonant clock. In a warm up stage, the last level clock driver can be enabled to store energy in the LC tank, and in a gating stage, the last level clock driver can be fully or partially disabled such that energy stored in the LC tank can be recirculated into a clock distribution network. In a refreshing stage, the last level clock driver can be enabled to replenish the energy lost by the LC tank in the recirculation of energy into the clock distribution network during the gating stage. Programmable counters can be used to control durations of the warm up, gating, and refreshing stages.Type: ApplicationFiled: September 27, 2014Publication date: March 31, 2016Inventors: Francois Ibrahim ATALLAH, David Joseph Winston HANSQUINE, Richard Duane TAX, Robert Simpson TAYLOR
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Publication number: 20160072491Abstract: Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems, are disclosed. The adaptive clock distribution system includes a tunable-length delay circuit to delay distribution of a clock signal provided to a clocked circuit, to prevent timing margin degradation of the clocked circuit after a voltage droop occurs in a power supply supplying power to the clocked circuit. The adaptive clock distribution system also includes a dynamic variation monitor to reduce frequency of the delayed clock signal provided to the clocked circuit in response to the voltage droop in the power supply, so that the clocked circuit is not clocked beyond its performance limits during a voltage droop. An automatic calibration circuit is provided in the adaptive clock distribution system to calibrate the dynamic variation monitor during operation based on operational conditions and environmental conditions of the clocked circuit.Type: ApplicationFiled: March 25, 2015Publication date: March 10, 2016Inventors: Keith Alan Bowman, Jeffrey Todd Bridges, Sarthak Raina, Yeshwant Nagaraj Kolla, Jihoon Jeong, Francois Ibrahim Atallah, William Robert Flederbach, Jeffrey Herbert Fischer
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Patent number: 9251875Abstract: A register file circuit according to some examples of the disclosure may include a memory cell, a header transistor circuit, and a driver circuit. The header transistor circuit may include one or more PFET headers in series with the PFETs of the memory cell with the gate of the PFET header for the row being written being controlled with a pulse write signal from the driver circuit. In some examples of the disclosure, the header transistor circuit may include an NFET pull-down inserted between a virtual-vdd and ground to discharge the virtual-vdd node reducing the contention during a write operation and a clamping NFET in parallel with the PFET header to clamp the virtual-vdd node to slightly below the threshold voltage of the pull-up PFET in the memory cell to ensure the pull-up PFET is barely off and prevent the virtual-vdd node from discharging all the way to ground.Type: GrantFiled: September 26, 2014Date of Patent: February 2, 2016Assignee: QUALCOMM IncorporatedInventors: Francois Ibrahim Atallah, Jihoon Jeong, Keith Alan Bowman, Amey Sudhir Kulkarni, Jason Philip Martzloff, Joshua Lance Puckett
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Patent number: 8615767Abstract: A data processing system having a memory for storing instructions and several central processing units for executing instructions, each central processing unit including an adaptive power supply which provides, among other data, IR (voltage) drop information. Circuitry is provided that receives the IR drop information from the many central processing units, selects a central processing unit which has the lowest IR drop and which is available to execute instructions and dispatches instructions to the selected central processing unit from the memory.Type: GrantFiled: February 6, 2007Date of Patent: December 24, 2013Assignee: International Business Machines CorporationInventors: Deepak K. Singh, Francois Ibrahim Atallah
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Patent number: 8515590Abstract: Measurement circuit components are included in an integrated circuit fabricated on a semiconductor substrate. A method is provided for controlling the speed of a cooling fan provided to cool an integrated circuit in which includes the steps of receiving a voltage from a thermal diode, addressing a table of digital temperatures by incrementing the address of the table entries every clock cycle of a circuit clock, converting the addressed data to a second voltage representing temperature, comparing the first voltage to the second voltage, providing a resulting temperature when both the first and second voltages are equal, and adjusting the fan speed accordingly.Type: GrantFiled: April 17, 2012Date of Patent: August 20, 2013Assignee: International Business Machines CorporationInventors: Deepak K. Singh, Francois Ibrahim Atallah, David Howard Allen
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Publication number: 20120203394Abstract: Measurement circuit components are included in an integrated circuit fabricated on a semiconductor substrate. A method is provided for controlling the speed of a cooling fan provided to cool an integrated circuit in which includes the steps of receiving a voltage from a thermal diode, addressing a table of digital temperatures by incrementing the address of the table entries every clock cycle of a circuit clock, converting the addressed data to a second voltage representing temperature, comparing the first voltage to the second voltage, providing a resulting temperature when both the first and second voltages are equal, and adjusting the fan speed accordingly.Type: ApplicationFiled: April 17, 2012Publication date: August 9, 2012Inventors: Deepak Singh, Francois Ibrahim Atallah, David Howard Allen
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Patent number: 8219261Abstract: Measurement circuit components are included in an integrated circuit fabricated on a semiconductor substrate. A method is provided for controlling the speed of a cooling fan provided to cool an integrated circuit in which includes the steps of receiving a voltage from a thermal diode, addressing a table of digital temperatures by incrementing the address of the table entries every clock cycle of a circuit clock, converting the addressed data to a second voltage representing temperature, comparing the first voltage to the second voltage, providing a resulting temperature when both the first and second voltages are equal, and adjusting the fan speed accordingly.Type: GrantFiled: September 13, 2010Date of Patent: July 10, 2012Assignee: International Business Machines CorporationInventors: Deepak K. Singh, Francois Ibrahim Atallah, David Howard Allen
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Patent number: 8022685Abstract: A circuit and a method for regulating a voltage supply where the method includes the steps of concurrently measuring temperature, IR drop and frequency response within the circuit, adjusting voltage supplied to the circuit in response to the measured temperature, IR drop and frequency response, and determining a correction value based on the variance of the measured frequency response from an expected frequency response and providing a correction for subsequent predetermined frequency response values. The frequency response measurement is dependent upon the constant bandgap voltage source which may very according to temperature. Upon a determination that corrections may be required for the bandgap voltage source to compensate for temperature variations, the measurement process which uses the bandgap voltage source can be altered to compensate for the temperature variations.Type: GrantFiled: February 6, 2007Date of Patent: September 20, 2011Assignee: International Business Machines CorporationInventors: Deepak K. Singh, Francois Ibrahim Atallah
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Patent number: 7971035Abstract: A data processing system having a memory for storing instructions and several central processing units for executing instructions, each central processing unit includes an adaptive power supply which provides, among other data, temperature information. Circuitry is provided that receives the temperature information from the many central processing units, selects a central processing unit which has the lowest temperature and which is available to execute instructions and dispatches instructions to the selected central processing from the memory.Type: GrantFiled: February 6, 2007Date of Patent: June 28, 2011Assignee: International Business Machines CorporationInventors: Deepak K. Singh, Francois Ibrahim Atallah
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Patent number: 7936153Abstract: Measurement circuit components are included in an integrated circuit fabricated on a semiconductor substrate. These measurement circuits are connected to a voltage regulation circuit that provides the integrated circuit voltage source. These measurement circuits provide signals to control the voltage regulation circuit to adjust the voltage output to the integrated circuit based upon a measurement values obtained on the semiconductor device. These measurements include temperature and IR drop at locations on the semiconductor substrate, along with the frequency response of integrated circuit.Type: GrantFiled: February 6, 2007Date of Patent: May 3, 2011Assignee: International Business Machines CorporationInventors: Deepak K. Singh, Francois Ibrahim Atallah
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Patent number: 7865750Abstract: Measurement circuit components are included in an integrated circuit fabricated on a semiconductor substrate. A method is provided for controlling the speed of a cooling fan provided to cool an integrated circuit in which includes the steps of receiving a voltage from a thermal diode, addressing a table of digital temperatures by incrementing the address of the table entries every clock cycle of a circuit clock, converting the addressed data to a second voltage representing temperature, comparing the first voltage to the second voltage, providing a resulting temperature when both the first and second voltages are equal, and adjusting the fan speed accordingly.Type: GrantFiled: February 6, 2007Date of Patent: January 4, 2011Assignee: International Business Machines CorporationInventors: Deepak K. Singh, Francois Ibrahim Atallah, David Howard Allen
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Publication number: 20100332875Abstract: Measurement circuit components are included in an integrated circuit fabricated on a semiconductor substrate. A method is provided for controlling the speed of a cooling fan provided to cool an integrated circuit in which includes the steps of receiving a voltage from a thermal diode, addressing a table of digital temperatures by incrementing the address of the table entries every clock cycle of a circuit clock, converting the addressed data to a second voltage representing temperature, comparing the first voltage to the second voltage, providing a resulting temperature when both the first and second voltages are equal, and adjusting the fan speed accordingly.Type: ApplicationFiled: September 13, 2010Publication date: December 30, 2010Inventors: Deepak K. Singh, Francois Ibrahim Atallah, David Howard Allen
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Patent number: 7797131Abstract: A method and circuit are provided for measuring frequency response performance of an integrated circuit by providing a pulse having a rising edge and a falling edge where the pulse is provided to a plurality of serially connected components. The number of these components which have propagated the leading edge of the pulse before the occurrence of the falling edge provide a numeric indication of the circuit's frequency response and performance.Type: GrantFiled: August 24, 2007Date of Patent: September 14, 2010Assignee: International Business Machines CorporationInventors: Deepak K. Singh, Francois Ibrahim Atallah, David John Seman
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Patent number: 7779235Abstract: A method for dispatching instructions in the data processing system, having in memory for storing instructions and a plurality of central processing units, where each central processing unit includes a circuit to provide data indicating internal performance, the method having steps of receiving internal performance data signals from a pool of central processing units, selecting a central processing unit according to the received internal performance data and dispatching instructions from the memory to the selected central processing unit.Type: GrantFiled: February 6, 2007Date of Patent: August 17, 2010Assignee: International Business Machines CorporationInventors: Deepak K. Singh, Francois Ibrahim Atallah
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Patent number: 7714635Abstract: Measurement circuit components are included in an integrated circuit fabricated on a semiconductor substrate. These measurement circuits include registers that are connected to a voltage regulation circuit that provides the integrated circuit voltage source and to a power management circuit. These measurement circuits provide signals to control the voltage regulation circuit for adjusting the voltage output to the integrated circuit based upon a measurement values obtained on the semiconductor device. These measurements include temperature, IR drop at locations on the semiconductor substrate, along with the frequency response of integrated circuit.Type: GrantFiled: February 6, 2007Date of Patent: May 11, 2010Assignee: International Business Machines CorporationInventors: Deepak K. Singh, Francois Ibrahim Atallah, David John Seman
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Publication number: 20090055122Abstract: A method and circuit are provided for measuring frequency response performance of an integrated circuit by providing a pulse having a rising edge and a falling edge where the pulse is provided to a plurality of serially connected components. The number of these components which have propagated the leading edge of the pulse before the occurrence of the falling edge provide a numeric indication of the circuit's frequency response and performance.Type: ApplicationFiled: August 24, 2007Publication date: February 26, 2009Applicant: International Business Machines CorportationInventors: Deepak K. Singh, Francois Ibrahim Atallah, David John Seman
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Publication number: 20080186001Abstract: Measurement circuit components are included in an integrated circuit fabricated on a semiconductor substrate. These measurement circuits are connected to a voltage regulation circuit that provides the integrated circuit voltage source. These measurement circuits provide signals to control the voltage regulation circuit to adjust the voltage output to the integrated circuit based upon a measurement values obtained on the semiconductor device. These measurements include temperature and IR drop at locations on the semiconductor substrate, along with the frequency response of integrated circuit.Type: ApplicationFiled: February 6, 2007Publication date: August 7, 2008Inventors: Deepak K. Singh, Francois Ibrahim Atallah