Abstract: Provided herein are methods and composition for immune repertoire sequencing and single cell barcoding. The methods and compositions can be used to pair any two sequences originating from a single cell, such as heavy and light chain antibody sequences, alpha and beta chain T-cell receptor sequences, or gamma and delta chain T-cell receptor sequences, for antibody and T-cell receptor discovery, disease and immune diagnostics, and low error sequencing.

Abstract: An apparatus for thermally processing food products in sealed packages comprises heating/cooling chambers with an endless conveyor guided through them with product carriers connected thereto. Each product carrier 10 comprises insertion spaces 17 for packages 27 to be placed in. A side wall 11 of the carrier 10 comprises slits 20 which open out towards insertion openings of the respective insertion spaces 17. Operating members are provided which comprise load bearing organs 32 with operable holding means 33 for picking up and carrying packages 27. The load bearing organs 32 are movable in an insertion direction x while projecting through the slits 20 during placing of packages 27 into the insertion spaces 17.

Abstract: An apparatus for thermally processing food products in sealed packages comprises heating/cooling chambers with an endless conveyor guided through them with product carriers connected thereto. Each product carrier 10 comprises insertion spaces 17 for packages 27 to be placed in. A side wall 11 of the carrier 10 comprises slits 20 which open out towards insertion openings of the respective insertion spaces 17. Operating members are provided which comprise load bearing organs 32 with operable holding means 33 for picking up and carrying packages 27. The load bearing organs 32 are movable in an insertion direction x while projecting through the slits 20 during placing of packages 27 into the insertion spaces 17.

Abstract: A method for detecting lack of synchronism during high level simulation of VLSI designs in which asynchronous clock domains (100 and 110) must coexist, which does not require knowledge of hardware target technology delays, and can be carried out by a small computer. The circuit design simulator is adapted to apply a value (A) representative of an unstable state to clock domain interface outputs (O′1) at each pulse of the clocks (clock 1) associated to clock domains used as interface inputs (100), during a predetermined time (TA). Thus, even though unstable states are very short regarding the clock periods and so are very difficult to detect in simulation, the method of the invention allows for detection of all potential synchronism failures. When sampling the value representative of an unstable state, the simulator may forewarn the user, store information and/or launch a standard local static analysis to determine whether or not the detected potential synchronism failure is a circuit design bug.

Abstract: A method for detecting lack of synchronism during high level simulation of VLSI designs in which asynchronous clock domains (100 and 110) must coexist, which does not require knowledge of hardware target technology delays, and can be carried out by a small computer. The circuit design simulator is adapted to apply a value (A) representative of an unstable state to clock domain interface outputs (O′1) at each pulse of the clocks (clock 1) associated to clock domains used as interface inputs (100), during a predetermined time (TA). Thus, even though unstable states are very short regarding the clock periods and so are very difficult to detect in simulation, the method of the invention allows for detection of all potential synchronism failures. When sampling the value representative of an unstable state, the simulator may forewarn the user, store information and/or launch a standard local static analysis to determine whether or not the detected potential synchronism failure is a circuit design bug.

Abstract: A fan system to be mounted over an opening including a plurality of pivoting blades fixed on a free wheeling element and a motor driven element wherein, in operation, when the fan is operating the motor driven element pivots the blades to a blowing position allowing air flow through the opening, and when the fan is not operating a resilient member pivots the blades to a closed position preventing air flow through the opening.

Abstract: The object of the present invention is to improve the execution of instructions using speculative operations in Superscalar or Very Long Instruction Word (VLIW) processors having multiple Arithmetic Logic Units (ALUs). More particularly, the invention relates to a system and method for using standard registers as shadow registers. The addresses of all standard registers are translated using a Relocation Table (RT) array. The addresses of registers used as shadow registers are translated another time using a Speculative Registers Table (SRT) array. At branch completion time, for the speculative operations that have previously been executed and correctly predicted, the Relocation Table (RT) is updated with the Speculative Registers Table (SRT) content. For the speculative operations that have previously been executed and incorrectly predicted, the Relocation Table (RT) remains unchanged.

Abstract: Processing system for interpreting and carrying out a set of logically related instructions stored into a software program, the execution of a given instruction by the processing system involving the decoding and the execution of a corresponding set of microcommands. The processing system stores a signature portion corresponding to the macrocommand portion of a given instruction which is to be interpreted and executed, and signature data in response to the actual decoding and execution process of the microcommands involved in the execution of the instruction. The processing system further compares the computed signature data with the signature portion in order to detect the occurrence of an error in the decoding and execution process of the given instruction. In one embodiment of the invention, the processing system is such that one instruction is interpreted and executed in one elementary machine cycle.