Patents by Inventor Francois L'Hermite

Francois L'Hermite has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6477066
    Abstract: An apparatus for reducing audible noise in a power supply (16) is provided. The apparatus comprises a shaper circuit (258) located on the secondary side (204) of a transformer (200) that is operable to control the shape of the current through a primary side inductor (222). By changing the shape of the current, acoustical noise is reduced in the transformer (200).
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: November 5, 2002
    Assignee: Semiconductor Components Industries LLC
    Inventor: Francois L'Hermite
  • Patent number: 6469484
    Abstract: A regulator circuit (26) operates a switching power supply (10) in discontinuous conduction mode (DCM) by detecting the state of demagnetization of a transformer (16) of the switching power supply. When a primary current (Ip) reaches zero the voltage across a drain and a source of a switching transistor (18) drops off sharply generating a negative spike in voltage at gate voltage VG. The negative spike in voltage indicates the transformer of the switching power supply is demagnetized. The negative spike is detected by a comparator (44). The comparator provides a signal (DEMAG) to a PWM regulator (46) which provides a first control signal (Lc) to a first transistor (40), and a second control signal (Uc) to a second transistor (42). The first and second transistors turn ON and OFF to enable ON the switching transistor only after the transformer (16) is demagnetized to enable the switching power supply to operate in DCM.
    Type: Grant
    Filed: February 20, 2001
    Date of Patent: October 22, 2002
    Assignee: Semiconductor Components Industries LLC
    Inventors: Francois L′Hermite, Christophe Basso
  • Publication number: 20020080628
    Abstract: An apparatus for reducing audible noise in a power supply (16) is provided. The apparatus comprises a shaper circuit (258) located on the secondary side (204) of a transformer (200) that is operable to control the shape of the current through a primary side inductor (222). By changing the shape of the current, acoustical noise is reduced in the transformer (200).
    Type: Application
    Filed: April 2, 2001
    Publication date: June 27, 2002
    Applicant: Semiconductor Components Industries, LLC.
    Inventor: Francois L'Hermite
  • Publication number: 20020070720
    Abstract: A regulator circuit (26) operates a switching power supply (10) in discontinuous conduction mode (DCM) by detecting the state of demagnetization of a transformer (16) of the switching power supply. When a primary current (IP) reaches zero the voltage across a drain and a source of a switching transistor (18) drops off sharply generating a negative spike in voltage at gate voltage VG. The negative spike in voltage indicates the transformer of the switching power supply is demagnetized. The negative spike is detected by a comparator (44). The comparator provides a signal (DEMAG) to a PWM regulator (46) which provides a first control signal (LC) to a first transistor (40), and a second control signal (UC) to a second transistor (42). The first and second transistors turn ON and OFF to enable ON the switching transistor only after the transformer (16) is demagnetized to enable the switching power supply to operate in DCM.
    Type: Application
    Filed: February 20, 2001
    Publication date: June 13, 2002
    Applicant: Semiconductor Components Industries, LLC
    Inventors: Francois L'Hermite, Christophe Basso
  • Patent number: 6392906
    Abstract: A pwm controller 10 which includes a Vcc node (pin 6); a start-up current source 180 connected to the Vcc node; and a driver circuit 150, 190 also connected to the Vcc node, wherein the pwm controller 10 is arranged to operate in a first phase in which the start-up current source supplies 180 current to the Vcc node but the driver circuit is turned off; a second phase in which the driver circuit 150, 190 is enabled and draws current from the Vcc node; and a third phase in which both the start-up current source 180 and the driver circuit 150, 190 are turned off whereby very little current may be drawn from the Vcc node (pin 6) during the third phase.
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: May 21, 2002
    Assignee: Semiconductor Components Industries LLC
    Inventors: Francois L'Hermite, Joel Turchi, Josef Halamik
  • Publication number: 20020018352
    Abstract: A pwm controller 10 which includes a Vcc node (pin 6); a start-up current source 180 connected to the Vcc node; and a driver circuit 150, 190 also connected to the Vcc node, wherein the pwm controller 10 is arranged to operate in a first phase in which the start-up current source supplies 180 current to the Vcc node but the driver circuit is turned off; a second phase in which the driver circuit 150,190 is enabled and draws current from the Vcc node; and a third phase in which both the start-up current source 180 and the driver circuit 150,190 are turned off whereby very little current may be drawn from the Vcc node (pin 6) during the third phase.
    Type: Application
    Filed: May 26, 2000
    Publication date: February 14, 2002
    Inventors: Francois L'Hermite, Joel Turchi, Josef Halamik
  • Patent number: 6208538
    Abstract: A Pulse Width Modulation (PWM) control circuit is used in a switched-mode power supply (SMPS) having a normal mode and a standby mode, for controlling and regulating the SMPS. An input of the PWM control circuit is arranged to receive a signal indicating an amount of current supplied by the supply. An over-current determining arrangement provides an over-current signal in the event of there being an over-current condition in the signal indicating the amount of current supplied by the supply. A further input of the PWM control circuit receives a regulation signal in the event of there being a regulation output from circuitry coupled to receive power from the SMPS. A logic circuit within the PWM control circuit compares the over-current signal and the regulation signal in order to determine whether the switched-mode power supply is in standby mode or normal mode, thus avoiding the need for a dedicated control pin to indicate standby and normal modes.
    Type: Grant
    Filed: June 1, 2000
    Date of Patent: March 27, 2001
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Josef Halamik, Francois L'Hermite, Joel Turchi
  • Patent number: 6177782
    Abstract: A power factor correction controller circuit 100 for controlling the duration of each on time phase and off time phase of a switched inductor power factor correction circuit 20, 30, 40, 50, 100 which is adapted for use with a rectifying arrangement 9, 10, 60, 70 producing a substantially regulated output voltage, Vo. The controller circuit 100 comprises an input terminal 114 for receiving a signal representative of Vo; an output terminal 131 for outputting a signal representative of the duration of each on time phase and off time phase; and on time determination means 110, 111, 112, 113, 114, 115, 116, 117; wherein the on time determination means acts to vary the maximum duration of each on time phase in an inverse dependence on Vo.
    Type: Grant
    Filed: April 23, 1999
    Date of Patent: January 23, 2001
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Francois L'Hermite, Joel Turchi
  • Patent number: 5471167
    Abstract: A feedback circuit (10) for use with a feedback arrangement includes an input terminal (12) for receiving a feedback signal from an output of the feedback arrangement. An output terminal (14) is coupled to a regulating arrangement of the feedback arrangement. A sampling arrangement (16) is coupled to the input terminal for providing a delayed feedback signal. A further arrangement (18,20,22,24,26,28) is coupled to the output terminal (14) for comparing the feedback signal with the delayed feedback signal and with a predetermined reference signal, such that the further arrangement (18,20,22,24,26,28) disables the regulating arrangement if a certain relationship exists between the compared signals.
    Type: Grant
    Filed: August 3, 1994
    Date of Patent: November 28, 1995
    Assignee: Motorola, Inc.
    Inventors: Francois L'Hermite, Joel Turchi