Abstract: A computing system can include a first system on chip (SoC) and a second SoC. Each SoC can comprise a memory in which the SoC publishes state information. For the first SoC, the state information can correspond to a set of tasks being performed by the first SoC, where the first SoC utilizes a plurality of computational components to perform the set of tasks. The first SoC can directly access the memory of the first SoC to dynamically read the state information published by the first SoC. In a backup role, the second SoC maintains a subset of its computational components in a low power state. When the second SoC detects a trigger while reading the state information published in the first memory of the first SoC, the second SoC powers the subset of computational components to take over the set of tasks.

Abstract: A computing system can include a sensor data input chiplet to obtain sensor data from a sensor system, a set of workload processing chiplets, and a central chiplet comprising a shared memory including a scheduling program for scheduling a set of runnables to execute based at least partially on the sensor data, where the set of runnables are included in a software structure. the set of runnables can be executed by the set of workload processing chiplets. Each runnable and each connection between runnables in the set of runnables can be associated with a safety rating to facilitate degradation of execution of the software structure.

Abstract: A computing system can execute a heuristic technique (e.g., traveling salesman algorithm) and/or a learning-based technique to determine an optimal distribution of compute tasks for execution on a given hardware topology.

Abstract: A sensor data input chiplet obtains sensor data from a sensor system. A central chiplet executes a functional safety program to dynamically compare and verify output of workloads being executed by a set of workload processing chiplets, where the workloads are executed across the set of workload processing chiplets based on the sensor data.

Abstract: A method of runtime program verification receives, through a preemptive mechanism of an operating system running on an external system, recent values for a set of system health indicators for the external system. The recent values are compared to calibrated values for the set of system health indicators, and normal operation of the external system is verified based on whether the comparison of the recent values to the calibrated values are within predetermined error thresholds.

Abstract: A system-on-chip (SoC) designed for an autonomous vehicle includes a central chiplet to coordinate the operations of the SoC constituent chiplets. The central chiplet includes a shared memory storing a number of programs associated with parallel workload pipelines, one or more processors to execute a scheduling program, and a cache memory accessible by the chiplets of the SoC. The SoC also includes a sensor data input chiplet to receive sensor data from vehicle sensors and store the sensor data in the cache memory. The scheduling program running on the central chiplet schedules the programs and causes respective workloads of the parallel workload pipelines to execute based, at least in part, on the sensor data stored in the cache memory.

Abstract: A computing system includes a sensor data input chiplet to obtain sensor data from a sensor system of a vehicle, and one or more workload processing chiplets executing workloads in a set of independent pipelines based on the sensor data.

Abstract: A computing system can include a sensor data input chiplet to (i) obtain sensor data from a sensor system, and (ii) store the sensor data in a cache. One or more workload processing chiplets can perform out-of-order execution on workloads corresponding to the sensor data stored in the cache, where respective workloads comprise sets of dependencies. The one or more workload processing chiplets perform out-of-order execution on the workloads by dynamically determining whether one or more dependencies exists for the respective workload, and when no data dependencies exist for the respective workload, executing the respective workload.

Abstract: A system on chip (SoC) can include a central chiplet with a functionally safe shared memory through which other chiplets of the SoC communicate. The SoC can also include a cache memory accessible by the chiplets, a sensor input chiplet to receive sensor data from sensors and store the sensor data in the cache memory, a machine learning accelerator chiplet to calculate inferences using machine learning, and an autonomous drive chiplet to calculate autonomous driving algorithms.

Abstract: A computing system can include a first system on chip (SoC) and a second SoC. Each SoC can comprise a memory in which the SoC publishes state information. For the first SoC, the state information can correspond to a set of tasks being performed by the first SoC, where the first SoC utilizes a plurality of computational components to perform the set of tasks. The first SoC can directly access the memory of the first SoC to dynamically read the state information published by the first SoC. In a backup role, the second SoC maintains a subset of its computational components in a low power state. When the second SoC detects a trigger while reading the state information published in the first memory of the first SoC, the second SoC powers the subset of computational components to take over the set of tasks.

Abstract: A system-on-chip can include a data input chiplet to obtain data from one or more data sources. The system-on-chip can further include one or more workload processing chiplets that access the data obtained by the data input chiplet to execute respective workloads. The system-on-chip further includes a central chiplet including a shared memory comprising a reservation table listing a plurality of workload entries. Each respective workload entry can correspond to a specified workload to be executed by the one or more workload processing chiplets. The central chiplet can input a thread number for each respective workload entry in the reservation table, where the thread number identifies a workload pipeline in which the specified workload is to be executed.

Abstract: Subject matter disclosed herein may relate to systems, devices and/or processes for extracting one or more features of an electric current coupled to an electric vehicle in response to initiating a charging process at a first charging station, determining one or more performance characteristics of the electric vehicle based, at least in part, on the charging process, determining a charge performance model based, at least in part, on the one or more determined one or more performance characteristics of the electric vehicle and displaying a recommendation for at least a second charging station based, at least in part, on a comparison between one or more features of the at least the second charging station and the charge performance model.