Patents by Inventor Francois Roy
Francois Roy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12677077Abstract: An image sensor includes a pixel array where each pixel is formed in a portion of a substrate electrically insulated from other portions of the substrate. Each pixel includes a photodetector; a transfer transistor; and a readout circuit comprising one or a plurality of transistors. The transistors of the readout circuit are formed inside and on top of at least one well of the portion. The reading from the photodetector of a pixel of a current row uses at least one transistor of the readout circuit of a pixel of at least one previous row, the well of the pixel of the previous row being biased with a first voltage greater than a second bias voltage of the well of the pixel of the current row.Type: GrantFiled: July 23, 2024Date of Patent: July 7, 2026Assignee: STMicroelectronics (Crolles 2) SASInventors: Francois Roy, Thomas Dalleau
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Patent number: 12543388Abstract: A photosensitive sensor includes a pixel formed by a photosensitive region in a first semiconductor material, a read region in a second semiconductor material, and a transfer gate facing the parts of the first semiconductor material and the second semiconductor material located between the photosensitive region and the read region. The first semiconductor material and the second semiconductor material have different band gaps and are in contact with one another to form a heterojunction facing the transfer gate.Type: GrantFiled: June 14, 2022Date of Patent: February 3, 2026Assignee: STMicroelectronics (Crolles 2) SASInventor: Francois Roy
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Patent number: 12538594Abstract: A sensor includes pixels supported by a substrate doped with a first conductivity type. Each pixel includes a portion of the substrate delimited by a vertical insulation structure with an image sensing assembly and a depth sensing assembly. The image sensing assembly includes a first region of the substrate more heavily doped with the first conductivity type and a first vertical transfer gate completely laterally surrounding the first region. Each of the depth sensing assemblies includes a second region of the substrate more heavily doped with the first conductivity type a second vertical transfer gate opposite a corresponding portion of the first vertical transfer gate. The second region is arranged between the second vertical transfer gate and the corresponding portion of the first vertical transfer gate.Type: GrantFiled: June 11, 2024Date of Patent: January 27, 2026Assignee: STMicroelectronics (Crolles 2) SASInventor: Francois Roy
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Publication number: 20260008296Abstract: A device for stretching a canvas mounted to at least a pair of side members includes a spacer having a central aperture therethrough and two opposing sides at an upper end that each terminate in a downwardly extending leg that is movable outwardly to engage an angled end surface of one of the side members. A screw engages the central aperture and has a threaded shaft that terminates at a screw head. At least one side wall is fixed with either the screw head or the spacer and is adapted for contacting the inside surface of each side member. In use, with the legs contacting the angled end surfaces, rotating the screw moves a spacer block to contact an inner surface of each leg to cause each leg to move outwardly to push the side members mutually away from each other to stretch the canvas.Type: ApplicationFiled: October 23, 2023Publication date: January 8, 2026Inventor: Francois Roy
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Patent number: 12471411Abstract: An optoelectronic device is manufactured by an epitaxial growth, on each first layer of many first layers spaced apart from each other on a first support, wherein the first is made of a first semiconductor material, of a second layer made of a second semiconductor material. A further epitaxial growth is made on each second layer of a stack of semiconductor layers. Each stack includes a third layer made of a third semiconductor material in physical contact with the second layer. Each stack is then separated from the first layer by removing the second layer using an etching that is selective simultaneously over both the first and third semiconductor materials. Each stack is then transferred onto a second support. Each of the first and third semiconductor materials is one of a III-V compound or a II-VI compound.Type: GrantFiled: April 27, 2023Date of Patent: November 11, 2025Assignee: STMicroelectronics (Crolles 2) SASInventor: Francois Roy
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Publication number: 20250338648Abstract: An electronic device includes a pixel. The pixel includes: a photodiode; a charge transfer channel including first and second semiconductor regions where the second region is separated from the photodiode by the first region; and a trench surrounding the channel where the trench includes first and second conductive core and an insulating sheath. The first core laterally surrounds the first region and the second core laterally surrounds, at least partially, the second region. A control method for pixel selectively biases the first and second cores to set electrostatic potentials of the first and second semiconductor regions during pixel integration (substantially equal and at a high value), pixel charge transfer (respectively at different first and second low values) and two steps of passing from pixel charge transfer to pixel readout (first at high and second low values respectively and then at the same high value).Type: ApplicationFiled: April 14, 2025Publication date: October 30, 2025Applicant: STMicroelectronics International N.V.Inventor: Francois ROY
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Patent number: 12336307Abstract: An electronic device is provided that includes a photodiode. The photodiode includes a semiconductor region coupled to a node of application of a first voltage, and at least one semiconductor wall. The at least one semiconductor wall extends along at least a height of the photodiode and partially surrounds the semiconductor region.Type: GrantFiled: June 23, 2022Date of Patent: June 17, 2025Assignee: STMicroelectronics (Crolles 2) SASInventors: Arnaud Tournier, Boris Rodrigues Goncalves, Francois Roy
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Publication number: 20240380999Abstract: An image sensor includes a pixel array where each pixel is formed in a portion of a substrate electrically insulated from other portions of the substrate. Each pixel includes a photodetector; a transfer transistor; and a readout circuit comprising one or a plurality of transistors. The transistors of the readout circuit are formed inside and on top of at least one well of the portion. The reading from the photodetector of a pixel of a current row uses at least one transistor of the readout circuit of a pixel of at least one previous row, the well of the pixel of the previous row being biased with a first voltage greater than a second bias voltage of the well of the pixel of the current row.Type: ApplicationFiled: July 23, 2024Publication date: November 14, 2024Applicant: STMicroelectronics (Crolles 2) SASInventors: Francois ROY, Thomas DALLEAU
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Publication number: 20240332324Abstract: A sensor includes pixels supported by a substrate doped with a first conductivity type. Each pixel includes a portion of the substrate delimited by a vertical insulation structure with an image sensing assembly and a depth sensing assembly. The image sensing assembly includes a first region of the substrate more heavily doped with the first conductivity type and a first vertical transfer gate completely laterally surrounding the first region. Each of the depth sensing assemblies includes a second region of the substrate more heavily doped with the first conductivity type a second vertical transfer gate opposite a corresponding portion of the first vertical transfer gate. The second region is arranged between the second vertical transfer gate and the corresponding portion of the first vertical transfer gate.Type: ApplicationFiled: June 11, 2024Publication date: October 3, 2024Applicant: STMicroelectronics (Crolles 2) SASInventor: Francois ROY
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Patent number: 12075178Abstract: An image sensor includes a pixel array where each pixel is formed in a portion of a substrate electrically insulated from other portions of the substrate. Each pixel includes a photodetector; a transfer transistor; and a readout circuit comprising one or a plurality of transistors. The transistors of the readout circuit are formed inside and on top of at least one well of the portion. The reading from the photodetector of a pixel of a current row uses at least one transistor of the readout circuit of a pixel of at least one previous row, the well of the pixel of the previous row being biased with a first voltage greater than a second bias voltage of the well of the pixel of the current row.Type: GrantFiled: November 14, 2022Date of Patent: August 27, 2024Assignee: STMicroelectronics (Crolles 2) SASInventors: Francois Roy, Thomas Dalleau
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Patent number: 12040335Abstract: A sensor includes pixels supported by a substrate doped with a first conductivity type. Each pixel includes a portion of the substrate delimited by a vertical insulation structure with an image sensing assembly and a depth sensing assembly. The image sensing assembly includes a first region of the substrate more heavily doped with the first conductivity type and a first vertical transfer gate completely laterally surrounding the first region. Each of the depth sensing assemblies includes a second region of the substrate more heavily doped with the first conductivity type a second vertical transfer gate opposite a corresponding portion of the first vertical transfer gate. The second region is arranged between the second vertical transfer gate and the corresponding portion of the first vertical transfer gate.Type: GrantFiled: September 14, 2022Date of Patent: July 16, 2024Assignee: STMicroelectronics (Crolles 2) SASInventor: Francois Roy
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Patent number: 11978756Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.Type: GrantFiled: December 21, 2020Date of Patent: May 7, 2024Assignee: STMicroelectronics (Crolles 2) SASInventors: Francois Roy, Sonarith Chhun
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Publication number: 20240128289Abstract: The present disclosure concerns an image sensor including a plurality of pixels, each including: a doped photosensitive region of a first conductivity type extending vertically in a semiconductor substrate; a charge collection region more heavily doped with the first conductivity type than the photosensitive region, extending vertically in the substrate from an upper surface of the substrate and being arranged above the photosensitive region; and a vertical stack including a vertical transfer gate and a vertical electric insulation wall, the stack crossing the substrate and being in contact with the charge collection region, the gate being arranged on the upper surface side of the substrate and penetrating into the substrate deeper than the charge collection region.Type: ApplicationFiled: December 20, 2023Publication date: April 18, 2024Applicant: STMicroelectronics (Crolles 2) SASInventors: Francois ROY, Andrej SULER
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Patent number: 11961868Abstract: A back side illuminated image sensor includes a pixel formed by three doped photosensitive regions that are superposed vertically in a semiconductor substrate. Each photosensitive region is laterally framed by a respective vertical annular gate. The vertical annular gates are biased by a control circuit during an integration phase so as to generate an electrostatic potential comprising potential wells in the central portion of the volume of each doped photosensitive region and a potential barrier at each interface between two neighboring doped photosensitive regions.Type: GrantFiled: May 17, 2023Date of Patent: April 16, 2024Assignee: STMicroelectronics (Crolles 2) SASInventor: Francois Roy
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Patent number: 11901381Abstract: The present disclosure concerns an image sensor including a plurality of pixels, each including: a doped photosensitive region of a first conductivity type extending vertically in a semiconductor substrate; a charge collection region more heavily doped with the first conductivity type than the photosensitive region, extending vertically in the substrate from an upper surface of the substrate and being arranged above the photosensitive region; and a vertical stack including a vertical transfer gate and a vertical electric insulation wall, the stack crossing the substrate and being in contact with the charge collection region, the gate being arranged on the upper surface side of the substrate and penetrating into the substrate deeper than the charge collection region.Type: GrantFiled: July 9, 2020Date of Patent: February 13, 2024Assignee: STMicroelectronics (Crolles 2) SASInventors: Francois Roy, Andrej Suler
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Publication number: 20230361241Abstract: An optoelectronic device is manufactured by an epitaxial growth, on each first layer of many first layers spaced apart from each other on a first support, wherein the first is made of a first semiconductor material, of a second layer made of a second semiconductor material. A further epitaxial growth is made on each second layer of a stack of semiconductor layers. Each stack includes a third layer made of a third semiconductor material in physical contact with the second layer. Each stack is then separated from the first layer by removing the second layer using an etching that is selective simultaneously over both the first and third semiconductor materials. Each stack is then transferred onto a second support. Each of the first and third semiconductor materials is one of a III-V compound or a II-VI compound.Type: ApplicationFiled: April 27, 2023Publication date: November 9, 2023Applicant: STMicroelectronics (Crolles 2) SASInventor: Francois ROY
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Publication number: 20230290801Abstract: A back side illuminated image sensor includes a pixel formed by three doped photosensitive regions that are superposed vertically in a semiconductor substrate. Each photosensitive region is laterally framed by a respective vertical annular gate. The vertical annular gates are biased by a control circuit during an integration phase so as to generate an electrostatic potential comprising potential wells in the central portion of the volume of each doped photosensitive region and a potential barrier at each interface between two neighboring doped photosensitive regions.Type: ApplicationFiled: May 17, 2023Publication date: September 14, 2023Applicant: STMicroelectronics (Crolles 2) SASInventor: Francois ROY
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Patent number: 11736826Abstract: A pixel includes: a detection node; a first normally on transistor connected between the detection node and a rail for applying a first potential; and a second transistor whose gate is connected to the detection node. An image sensor includes a plurality of the pixels and a control circuit configured to apply, during for a phase of initializing the detection node, the first potential to the gate of the first transistor.Type: GrantFiled: June 25, 2020Date of Patent: August 22, 2023Assignee: STMicroelectronics (Crolles 2) SASInventors: Francois Roy, Thomas Dalleau
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Patent number: 11695028Abstract: A semiconductor image sensor includes a plurality of pixels. Each pixel of the sensor includes a semiconductor substrate having opposite front and back sides and laterally delimited by a first insulating wall including a first conductive core insulated from the substrate, electron-hole pairs being capable of forming in the substrate due to a back-side illumination. A circuit is configured to maintain, during a first phase in a first operating mode, the first conductive core at a first potential and to maintain, during at least a portion of the first phase in a second operating mode, the first conductive core at a second potential different from the first potential.Type: GrantFiled: October 29, 2021Date of Patent: July 4, 2023Assignee: STMicroelectronics (Crolles 2) SASInventors: Francois Roy, Stephane Hulot, Andrej Suler, Nicolas Virollet
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Patent number: D1007875Type: GrantFiled: August 20, 2021Date of Patent: December 19, 2023Inventor: Francois Roy