Abstract: A data storage circuit includes a first memory array comprising a plurality of FeRAM memory units; a second memory array comprising a plurality of OxRAM memory units; each of the first and second memory arrays comprising: a plurality of word lines, a plurality of source lines and a plurality of bit lines; for each column each memory unit comprising: a memory cell having a first electrode and a second electrode connected to the source line associated to the memory unit; a selection transistor having a gate connected to the word line associated to the memory unit and placed in series with the memory cell between the source line and a bit line associated to of the memory unit; the data storage circuit comprising further: a data transfer stage configured to transfer data from a set of source FeRAM memory units having a common bit line to a target OxRAM unit by converting a read signal from the common bit line to a transfer voltage applied on a target line of the target OxRAM unit; the target line corresponding to

Abstract: A data storage circuit includes a first memory array comprising a plurality of FeRAM memory units; a second memory array comprising a plurality of OxRAM memory units; each of the first and second memory arrays comprising: a plurality of word lines, a plurality of source lines and a plurality of bit lines; for each column each memory unit comprising: a memory cell having a first electrode and a second electrode connected to the source line associated to the memory unit; a selection transistor having a gate connected to the word line associated to the memory unit and placed in series with the memory cell between the source line and a bit line associated to of the memory unit; the data storage circuit comprising further: a data transfer stage configured to transfer data from a set of source FeRAM memory units having a common bit line to a target OxRAM unit by converting a read signal from the common bit line to a transfer voltage applied on a target line of the target OxRAM unit; the target line corresponding to

Abstract: A processing system for processing signals from a plurality of transducers of an ultrasonic sensor in order to determine characteristic information relating to an object detected by the ultrasonic sensor is provided. The system comprises a coupling device for transforming the signals received from the transducers into pulses, and a pulse processing unit for determining the characteristic information based on the pulses delivered by the coupling device. The coupling device comprises: a thresholding unit for applying, for each signal received from a transducer, thresholding to a signal derived from the signal received from the transducer and extracting directional information contained in the phase of the derived signal; a transformation unit for transforming the derived signal into pulses containing the phase of the signal, using the information extracted by the thresholding unit.

Abstract: A Resistive random access memory (ReRAM) comprising: an array (M1) of cells (Cij) each connected to a first supply line (SL) set at a first supply potential, each cell being provided with a resistive element (1, 2) and a selection transistor (Ms1, Ms2), a read circuit (400) associated with a given row of cells and comprising a sense amplifier (440) of the latch type connected to a second supply line (45) set at a second supply potential, the device further comprising: a circuit for controlling read operations configured to during a reading: apply to said first bit line (BL0) a potential equal to said first supply potential (GND, VDD) while isolating the first bit line (BL0) from said sense amplifier (440), then, couple the first bit line (BL0) to said sense amplifier (440).

Abstract: A data storage circuit includes a matrix array of memory cells. The memory cells are configurable and non-volatile. Each one is intended to operate in either one of two operating configurations; the first operating configuration corresponding to a ferroelectric random-access memory; and the second operating configuration corresponding to a metal-oxide resistive random-access memory. Each memory cell comprises: a stack of thin layers in the following order: a first layer made of an electrically conductive material forming a lower electrode, a second layer made of a dielectric and ferroelectric material and a third layer made of electrically conductive material forming an upper electrode.

Abstract: A computer for executing a computation algorithm involving a digital variable as per at least two operating phases is provided. The computer includes a memory stage having: a first set of memories for storing a first sub-word of each digital variable; with each memory of the first set being non-volatile and having a first read endurance and a first write cyclability; a second set of memories for storing a second sub-word of each digital variable; with each memory of the second set having a second read endurance and a second write cyclability; with the first read endurance being greater than the second read endurance and the first write cyclability being less than the second write cyclability.

Abstract: An artificial neuron for a neuromorphic chip comprises a synapse with resistive memory representative of a synaptic weight. The artificial neuron comprises a read circuit, an integration circuit and a logic circuit interposed between the read circuit and the integration circuit. The read circuit is configured to impose on the synapse a read voltage independent of the membrane voltage and to provide an analogue value representative of the synaptic weight. The logic circuit is configured to generate from the analogue value a pulse having a duration. The integration circuit comprises an accumulator of synaptic weights at the terminals of which a membrane voltage is established and a comparator configured to emit a postsynaptic pulse if a threshold is exceeded by the membrane voltage. Moreover, it comprises a source of current controlled by the pulse to inject a current into the accumulator of synaptic weights during this duration.

Abstract: Circuit and method for controlling a resistive memory formed by resistive memory cells each provided with a resistive memory element associated in series with a selector, each cell implementing a coding referred to as “multi-level” coding and being programmed in a given programming state among k (with k>2) possible programming states, wherein during a read operation, a sequence of different read voltages are applied to the given cell, and at each applied read voltage it is detected whether the read current passing through said given cell consecutively to the application of said read voltage corresponds to a leakage current level of the selector when this selector is in an off state or to a current level when the selector is in an on state.

Abstract: A processing system for processing signals from a plurality of transducers of an ultrasonic sensor in order to determine characteristic information relating to an object detected by the ultrasonic sensor is provided. The system comprises a coupling device for transforming the signals received from the transducers into pulses, and a pulse processing unit for determining the characteristic information based on the pulses delivered by the coupling device. The coupling device comprises: a thresholding unit for applying, for each signal received from a transducer, thresholding to a signal derived from the signal received from the transducer and extracting directional information contained in the phase of the derived signal; a transformation unit for transforming the derived signal into pulses containing the phase of the signal, using the information extracted by the thresholding unit.

Abstract: A Resistive random access memory (ReRAM) comprising: an array (M1) of cells (Cij) each connected to a first supply line (SL) set at a first supply potential, each cell being provided with a resistive element (1, 2) and a selection transistor (Ms1, Ms2), a read circuit (400) associated with a given row of cells and comprising a sense amplifier (440) of the latch type connected to a second supply line (45) set at a second supply potential, the device further comprising: a circuit for controlling read operations configured to during a reading: apply to said first bit line (BL0) a potential equal to said first supply potential (GND, VDD) while isolating the first bit line (BL0) from said sense amplifier (440), then, couple the first bit line (BL0) to said sense amplifier (440).

Abstract: An artificial neuron for a neuromorphic chip comprises a synapse with resistive memory representative of a synaptic weight. The artificial neuron comprises a read circuit, an integration circuit and a logic circuit interposed between the read circuit and the integration circuit. The read circuit is configured to impose on the synapse a read voltage independent of the membrane voltage and to provide an analogue value representative of the synaptic weight. The logic circuit is configured to generate from the analogue value a pulse having a duration. The integration circuit comprises an accumulator of synaptic weights at the terminals of which a membrane voltage is established and a comparator configured to emit a postsynaptic pulse if a threshold is exceeded by the membrane voltage. Moreover, it comprises a source of current controlled by the pulse to inject a current into the accumulator of synaptic weights during this duration.

Abstract: A synaptic integration circuit for a neuromorphic chip comprising a resistive memory synapse which has an activation terminal to receive a presynaptic action signal and a propagation terminal intended to be connected to the circuit for transmitting a synaptic output signal which depends on the resistance of the memory. The circuit comprises an accumulator of the synaptic output signal, a comparator configured to emit a postsynaptic spike in case of the crossing of a threshold (Vm) by the accumulated output signal. It further comprises a control unit configured, when a presynaptic action signal is applied on the activation terminal, to impose a conductance modification voltage on the synapse by controlling the application of a postsynaptic action signal (VBLset, VBLreset) on the propagation terminal.

Abstract: An impulse-neuron-type neuromorphic circuit comprises a capacitor (Cmem) having a membrane voltage (Vmem), a first action comparator (1) for comparing the membrane voltage with a first action voltage (Vact, Vthreshold_high), a first regulation comparator (4) for comparing the membrane voltage with a first regulation voltage (Vreg), a device for reinitialising the membrane voltage (3) a register of threshold exceeds (5) and a regulator (2). The regulator is configured: in case of exceeding the first regulation voltage (Vreg Vthreshold_low) by the membrane voltage, to control the device for reinitialising the membrane voltage (3) and modify the register of threshold exceeds (5); and in case of exceeding the first action voltage (Vact Vthreshold_high) by the membrane voltage, to control the device for reinitialising the membrane voltage (3) and query the register of threshold exceeds to decide whether or not to generate an action potential (Spa) on an output of the neuromorphic circuit.

Abstract: The present invention relates to photovoltaic modules backsheets (10) on base of preferably high molecular weight, impact resistant, shrinkage and thermal (flow) resistant FPP (Flexible Polypropylene) compositions preferably containing functional particles or being coextruded with a primer adhesive layer (13a) to obtain highly reliable adhesion on EVA adhesive layers (5). In one embodiment, the backsheet (10) has a functional PO adhesive layer (13b) allowing direct adhesion to cells back-contacts, i.e. without the use of an EVA adhesive layer (5). In a further embodiment, the backsheet (10), with functional PO adhesive layer (13b), allows the use of an upper adhesive layer (2) which is a surface functionalized transparent TPO film.

Abstract: The present invention relates to profiles for attaching rigid plates, especially photovoltaic modules, to a roof and to a method and system for attaching photovoltaic modules to a roof structure with the help of profiles.

Abstract: A coextruded backsheet on base of TPO layers, mainly FPP based layers and heat resistant and barrier layers, where the FPP layers dominate in the tensile strength of the backsheet by addition of fillers and the FPP layers have excellent long term heat stability by addition of specific heat stabilizers. Thanks to its relative softness, the stresses on PV cells are reduced, compared to PET based backsheet. Advantageous combinations with VLDPE based encapsulants are described.

Abstract: A flexible, calenderable film exhibiting enhanced durability under external weathering conditions. The film comprises predominantly a base layer of a graft copolymer of vinyl chloride on polyacrylate laminated with an acrylic based protective layer. Importantly, the base layer is devoid or contains minimal plasticiser components to eliminate or reduce UV absorber migration from the acrylic based protective layer.

Abstract: The present invention relates to profiles for attaching rigid plates, especially photovoltaic modules, to a roof and to a method and system for attaching photovoltaic modules to a roof structure with the help of profiles.

Abstract: The present invention relates to profiles for attaching rigid plates, especially photovoltaic modules, to a roof and to a method and system for attaching photovoltaic modules to a roof structure with the help of profiles.

Abstract: The present invention relates to profiles for attaching rigid plates, especially photovoltaic modules, to a roof and to a method and system for attaching photovoltaic modules to a roof structure with the help of profiles.