Abstract: The present embodiments relate to buffering signals between disjointed power domains with similar power profiles in an integrated circuit. According to some aspects, embodiments relate to a method in which an electronic design automation (EDA) tool displays a schematic including a plurality of first power domains having a first power profile and a plurality of second power domains having a second power profile. The EDA tool generates graph including a plurality of points and a plurality of edges connecting the points, where the points are located on the plurality of second power domains. The EDA tool selects one route from a plurality of routes from a start node on the graph to an end node on the graph and determines a number of buffers located on the route based on associated distance values and a design violation values.

Abstract: A method of determining a useful skew for a circuit design includes computing a slack value for each sequential cell in the circuit design, identifying modifiable sequential cells in the circuit design, and computing a target delay for each modifiable sequential cell. One or more sequential cells are discarded based on the slack values. A target slack value for each remaining sequential cell is determined. The remaining cells are sorted based on the target slack values to determine a minimum target slack value, and a delay for each cell is determined based on the minimum target slack value.

Abstract: A method of determining a useful skew for a circuit design includes computing a slack value for each sequential cell in the circuit design, identifying modifiable sequential cells in the circuit design, and computing a target delay for each modifiable sequential cell. One or more sequential cells are discarded based on the slack values. A target slack value for each remaining sequential cell is determined. The remaining cells are sorted based on the target slack values to determine a minimum target slack value, and a delay for each cell is determined based on the minimum target slack value.

Abstract: Timing slack is allocated to edges of a timing graph by a converging loop that calls a Domain Restricted Timing Cone (DRTC) iterator. The DRTC iterator invokes a kernel program for each DRTC and computes time budgets for each edge. The time budgets are kept within established constraints of the corresponding DRTC. A timing verifier computes an amount of slack for each edge based on the time budget. An edge or arc of the timing graph is made permanent when the slack is less than a predetermined epsilon. The kernel program is based on any of a fast estimate, consideration of all time to end point (tte) and weight to endpoint (wte) pairs within the graph, and/or a set of tte wte pairs (or an envelope) that represent segments of a lowest slack to weight ratio.

Abstract: A method and a system implement a circuit design in an integrated chip. A floorplan of the circuit design is arranged at a high level of abstraction. The design is synthesized based on the floorplan, and the synthesized design is laid out physically on the integrated circuit.

Abstract: A set of flat net descriptors are added to a hierarchical representation of a specified circuit design so as to provide a hierarchical view and a flat net view of the circuit design. The hierarchical representation includes a set of cell descriptors representing hierarchical cells in the specified circuit design, and a set of net descriptors representing portions of interconnections located within each hierarchical cell. Each net descriptor has associated therewith a list of endpoint descriptors representing endpoints of a corresponding one of the interconnections located within a respective hierarchical cell. The procedure for generating flat nets generates a flat net descriptor for each interconnection in the specified circuit. Each flat net descriptor has associated therewith a list of endpoint descriptors representing all endpoints of the interconnection.

Abstract: A programmed design tool and method for determining the placement of components of a very large scale integrated circuit. The present invention is characterized by a common timing engine adapted to check front end high level timing constraints in relation to a netlist representing the circuit.

Abstract: A method and a system allocate a budget to a circuit design. A timing analysis is prepared for a circuit and a budget is automatically allocated to each of the blocks of the circuit.

Abstract: In a computer aided design system for assisting in the design and analysis of integrated circuits, users can specify an integrated circuit using either a conventional circuit component netlist, or an HDL circuit description. Timing constraints are specified using conventional system level timing constraints, at least one clock timing constraint and a plurality multi-cycle timing constraints specifying clock based timing constraints for the transmission of data between sequential data elements in which at least a subset of the clock based timing constraints concern timing constraints for duration longer than a single clock period. In addition, the user may provide the system with a plurality of constraint based timing path specifications, each indicating signal paths through the integrated circuit to which specified ones of the multi-cycle timing constraints are applicable and signal paths to which the specified ones of the multi-cycle timing constraints are not applicable.

Abstract: A method of designing a circuit is described. A netlist for a circuit is generated. An analysis of the netlist is then executed to generate a set of cell instance performance values that characterize the performance of multiple gate instance-level components of the circuit in view of a selected parameter, such as circuit timing, circuit power consumption, or circuit area. Relying upon the set of cell instance performance values, a problematic component within the circuit is identified for replacement. A set of functionally equivalent candidate components are then identified. Each candidate component is analyzed with respect to the selected parameter. The analysis identifies an optimally performing candidate component. An instance of the optimally performing candidate component is then substituted into the netlist for the problematic component to improve the performance of the circuit.

Abstract: Process for the processing of logic function specification data of an associated specific integrated circuit or ASIC for a graphical representation of said circuit. The process consists of associating with the specification data Boolean attributes as a function of aspects, characteristics and details which a user wishes to know with respect to the circuit and then constructing data representative of said characteristics. One representation of the circuit can then be displayed by associating graphical symbols with the constructed data.