Patents by Inventor Francois Trans

Francois Trans has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050186933
    Abstract: A system and method for delivering increases speed, security, and intelligence to wireline and wireless systems. The present invention includes a new generation Fast Circuit Switch (packet/circuit) Communication processors and platform which enables a new Internet Exchange Networking Processor Architecture at the edge and core of every communication system, for next generation Web Operating System or Environment (WOE) to operate on with emphasis of a non-local processor or networking processor with remote web computing capabilities.
    Type: Application
    Filed: February 23, 2005
    Publication date: August 25, 2005
    Inventor: Francois Trans
  • Patent number: 6904110
    Abstract: A system and method for delivering increases speed, security, and intelligence to wireline and wireless systems. The present invention increases channel capacity by using a parallel or multi-channel structure in such wireless and wireline at the edge or the core of. This new architecture of the present invention uses parallel bitstreams in a flexible way and distributed switching/routing technique, is not only to avoid the potential bottlenet of centralized switches, but also to increase speed with intelligence that is seamlessly integrating into the Fiber Optic Backbone such as WDM and SONET of the MAN/WAN network with a Real-time guarantees, different types of traffic (such as Stringent synchronous, isochronous, and asynchronous data messages) with different demands, and privacy & security of multi access and integrated services environment.
    Type: Grant
    Filed: May 1, 2001
    Date of Patent: June 7, 2005
    Inventors: Francois Trans, Tho Le-Ngoc
  • Publication number: 20030128781
    Abstract: The DPIC makes use of the D detected symbols from the output of the Slicer to estimate the precursor ISI which still exists at the input sample of the Slicer. The estimation of the residual ISI value is done by a D-tap Finite Impulse Filter (FIR). This D-tap FIR has the same structure as the DFE or the Echo or NEXT canceller except the values of the coefficients. Since it calculates, A D-symbol delay element is used to keep the DT-delayed sample, from which the corresponding residual precursor ISI computed the D-tap FIR, is removed.
    Type: Application
    Filed: January 13, 2003
    Publication date: July 10, 2003
    Inventors: Tho Le-Ngoc, Francois Trans
  • Publication number: 20030086515
    Abstract: A system and method for delivering increased speed, security, and intelligence to wireline and wireless systems. The present invention includes a new generation Fast Circuit Switch (packet/circuit) Communication processors and platform which enables a new Internet Exchange Networking Processor Architecture at the edge and core of every communication system, for next generation Web Operating System or Environment (WOE) to operate on with emphasis of a non-local processor or networking processor with remote web computing capabilities.
    Type: Application
    Filed: October 3, 2001
    Publication date: May 8, 2003
    Inventors: Francois Trans, Tho L. Ngoc
  • Patent number: 6553085
    Abstract: In a bidirectional data channel between a central station and a multiple of remote stations, a method for equalizing interference over a synchronized packet or frame based baseband transmission system wherein the crosstalk on the system is cyclostationary or periodic with a period equal to a symbol interval, the method comprising the steps of synchronizing the transmitters and receivers using the uncorrelated transmit signals; generating the cyclostationary NEXT and FEXT interference along with ISI using the uncorrelated symbols at the synchronized transmitters at one or more remote stations and the centrally station; using cascaded Fractionally Spaced Linear Equalizer (FSLE) and Decision Feed back Equalizer (DFE) for both interference suppression and equalization to minimize excess bandwidth at central receivers at the central station; increasing the receiver's FSLE filter taps (NT) to maximize Signal to noise ration; combining FSLE/DFE and proper phase sampling adjustments, enabling use of the spectral
    Type: Grant
    Filed: October 13, 1999
    Date of Patent: April 22, 2003
    Inventor: Francois Trans
  • Publication number: 20030016770
    Abstract: A system and method for delivering increases speed, security, and intelligence to wireline and wireless systems. The present invention includes a new generation Fast Circuit Switch (packet/circuit) Communication processors and platform which enables a new Internet Exchange Networking Processor Architecture at the edge and core of every communication system, for next generation Web Operating System or Environment (WOE) to operate on with emphasis of a non-local processor or networking processor with remote web computing capabilities.
    Type: Application
    Filed: May 1, 2001
    Publication date: January 23, 2003
    Inventors: Francois Trans, Tho Le-Ngoc
  • Publication number: 20020181633
    Abstract: Nodes on a network are synchronized with each other using a clock transfer system. The communications channels between the nodes are then measured and calibrated for optimal bandwidth. The optimized channels and synchronization enables a new form of signaling based on precise control of the frequency, amplitude, and phase of the waveform of the signal. Receiving nodes receive information in order to locate the signal at the appropriate frequency, phase and amplitude. Precision control of these parameters also servers as a unique signature of the transmitting node preventing security breaches as the signal's characteristic are unique to the transmitting node. The channel is continuously updated with a precision control system to insure that the nodes are not out of phase.
    Type: Application
    Filed: March 11, 2002
    Publication date: December 5, 2002
    Inventor: Francois Trans
  • Patent number: 6377640
    Abstract: Nodes on a network are synchronized with each other using a clock transfer system. The communications channels between the nodes are then measured and calibrated for optimal bandwidth. The optimized channels and synchronization enables a new form of signaling based on precise control of the frequency, amplitude, and phase of the waveform of the signal. Receiving nodes receive information in order to locate the signal at the appropriate frequency, phase and amplitude. Precision control of these parameters also servers as a unique signature of the transmitting node preventing security breaches as the signal's characteristic are unique to the transmitting node. The channel is continuously updated with a precision control system to insure that the nodes are not out of phase.
    Type: Grant
    Filed: July 31, 1998
    Date of Patent: April 23, 2002
    Assignee: Stanford Syncom, Inc.
    Inventor: Francois Trans
  • Publication number: 20010038674
    Abstract: Nodes on a network are synchronized with each other using a clock transfer system. The communications channels between the nodes are then measured and calibrated for optimal bandwidth. The optimized channels and synchronization enables a new form of signaling based on precise control of the frequency, amplitude, and phase of the waveform of the signal. Receiving nodes receive information in order to locate the signal at the appropriate frequency, phase and amplitude. Precision control of these parameters also servers as a unique signature of the transmitting node preventing security breaches as the signal's characteristic are unique to the transmitting node. The channel is continuously updated with a precision control system to insure that the nodes are not out of phase.
    Type: Application
    Filed: July 31, 1998
    Publication date: November 8, 2001
    Inventor: FRANCOIS TRANS