Abstract: Methods for selecting the best measurement sites for OPC model calibration are disclosed. Embodiments include selecting a predetermined number, n, of structures representing an IC design layout eligible for SEM measurement; specifying an image parameter space of image parameters for the n structures; optimizing a redundancy in the image parameter space of measurement sites for the n structures; and calibrating an OPC model for the IC design layout based on the optimized redundancy.

Abstract: Geometrically-defined kernels are applied along each point of a lithographic contour to derive etch parameters that can be used to characterize the etch response of any structure. The etch parameters can be further used to construct an accurate etch model. The approach provides a more detailed definition of the etch parameter space and results in better guidance for selecting optimal calibration structures.

Abstract: Methods for selecting the best measurement sites for OPC model calibration are disclosed. Embodiments include selecting a predetermined number, n, of structures representing an IC design layout eligible for SEM measurement; specifying an image parameter space of image parameters for the n structures; optimizing a redundancy in the image parameter space of measurement sites for the n structures; and calibrating an OPC model for the IC design layout based on the optimized redundancy.

Abstract: Methods for selecting the best measurement sites for OPC model calibration are disclosed. Embodiments include selecting a predetermined number, n, of structures representing an IC design layout eligible for SEM measurement; specifying an image parameter space of image parameters for the n structures; optimizing a redundancy in the image parameter space of measurement sites for the n structures; and calibrating an OPC model for the IC design layout based on the optimized redundancy.

Abstract: A method of determining an average contour of a patterned feature on a wafer includes providing a reference contour corresponding to the patterned feature on the wafer, providing a plurality of images of the patterned feature, extracting from the plurality of images a plurality of extracted contours that represent the patterned feature, eliminating flyers from the plurality of extracted contours, and generating the average contour of the patterned feature based on the extracted contours remaining after elimination of the flyers.

Abstract: Methods for selecting the best measurement sites for OPC model calibration are disclosed. Embodiments include selecting a predetermined number, n, of structures representing an IC design layout eligible for SEM measurement; specifying an image parameter space of image parameters for the n structures; optimizing a redundancy in the image parameter space of measurement sites for the n structures; and calibrating an OPC model for the IC design layout based on the optimized redundancy.

Abstract: A method of determining an average contour of a patterned feature on a wafer includes providing a reference contour corresponding to the patterned feature on the wafer, providing a plurality of images of the patterned feature, extracting from the plurality of images a plurality of extracted contours that represent the patterned feature, eliminating flyers from the plurality of extracted contours, and generating the average contour of the patterned feature based on the extracted contours remaining after elimination of the flyers.

Abstract: Variations in critical dimensions of circuit features of sophisticated semiconductor devices may be reduced by efficiently extracting mask and/or imaging tool specific non-uniformities with high spatial resolution by using measured intensity values and simulated intensity values. For example, a tool internal radiation sensor may be used for measuring the intensity of an image of a lithography mask, while a simulated intensity enables eliminating the mask pattern specific intensity contributions. In this manner, high spatial resolution of the corresponding correction map may be obtained without undue effort in terms of man power and measurement tool resources.

Abstract: Variations in critical dimensions of circuit features of sophisticated semiconductor devices may be reduced by efficiently extracting mask and/or imaging tool specific non-uniformities with high spatial resolution by using measured intensity values and simulated intensity values. For example, a tool internal radiation sensor may be used for measuring the intensity of an image of a lithography mask, while a simulated intensity enables eliminating the mask pattern specific intensity contributions. In this manner, high spatial resolution of the corresponding correction map may be obtained without undue effort in terms of man power and measurement tool resources.