Abstract: An integrated circuit comprising at least one processing module (PROC) for processing an application (APL) requiring specific communication parameter, at least one dynamic random access memory means (MM) for storing data, wherein the memory means (MM) is operable by a plurality of predefined operating modes, is provided. Additionally, at least one memory access selection means (SM) for selecting one of said plurality of predefined operating modes based on said communication parameters and at least one memory controller (MC) for controlling the access of said at least one dynamic random access memory means (MM) according to said predefined operating modes selected by said memory access selecting means (SM) is provided. Each of said memory controller (MC) are associated to one of the dynamic random access means (MM). An interconnect means (IM) couples the processing modules (PROC) and the memory controller (MC), such that the communication over the interconnect means (IM) is achieved.

Abstract: An integrated circuit comprising a plurality of modules (M) for processing applications is provided, wherein each of said modules comprise a local memory (LM). The integrated circuit further comprises a global memory (GM), which can be shared between the plurality of modules (M), and an interconnect means (IM) for interconnecting said modules (M) and said global memory (GM). A memory managing unit (MMU) is associated to each of said modules (M) and determines whether the local memory (LM) provides sufficient memory space for the currently processed application. If this is not the case, the memory managing unit (MMU) requests a global buffer (FB) in said global memory (GM) to be exclusively reserved for the processing data of its associated module (M). Accordingly, by using the local memory (LM), whenever possible, before data is outsourced to the global memory (GM), power as well as bandwidth of the interconnect means can be saved.

Abstract: An integrated circuit comprising a plurality of modules (M1 to M5, CPU) for processing applications, a global memory (GM), which can be shared by said plurality of modules (M1 to M5, CPU), an interconnect means (IM) for interconnecting said modules (M1 to M5, CPU) and said global memory (GM) based on a plurality of communication services (C1, C2) is provided. Said integrated circuit further comprises at least one communication managing unit (CMU) for managing the communication between said plurality of modules (M1 to M5), wherein said communication managing unit (CMU) receives a request for a communication between at least two of said modules (M1 to M5, CPU) and dynamically selects one of said plurality of communication services (C1, C2) as basis for the requested communication between said modules (MI to M5, CPU).