Abstract: Certain aspects of the disclosure are directed to in-phase/quadrature (IQ) mismatch detection and correction in radio frequency receivers. According to a specific example, a method of manufacture or use comprises, in a quadrature radio-frequency receiver configured to process signals using I and Q components, providing parameters indicative of IQ mismatches associated with circuitry of the quadrature radio-frequency receiver due to changes in signal gain. The method further includes, while using the quadrature radio-frequency receiver to receive and process a received radio signal, correcting for the IQ mismatches by using the parameters in response to actual signal gain change.

Abstract: Certain aspects of the disclosure are directed to in-phase/quadrature (IQ) mismatch detection and correction in radio frequency receivers. According to a specific example, a method of manufacture or use comprises, in a quadrature radio-frequency receiver configured to process signals using I and Q components, providing parameters indicative of IQ mismatches associated with circuitry of the quadrature radio-frequency receiver due to changes in signal gain. The method further includes, while using the quadrature radio-frequency receiver to receive and process a received radio signal, correcting for the IQ mismatches by using the parameters in response to actual signal gain change.

Abstract: An integrated circuit comprising a plurality of modules (M) for processing applications is provided, wherein each of said modules comprise a local memory (LM). The integrated circuit further comprises a global memory (GM), which can be shared between the plurality of modules (M), and an interconnect means (IM) for interconnecting said modules (M) and said global memory (GM). A memory managing unit (MMU) is associated to each of said modules (M) and determines whether the local memory (LM) provides sufficient memory space for the currently processed application. If this is not the case, the memory managing unit (MMU) requests a global buffer (FB) in said global memory (GM) to be exclusively reserved for the processing data of its associated module (M). Accordingly, by using the local memory (LM), whenever possible, before data is outsourced to the global memory (GM), power as well as bandwidth of the interconnect means can be saved.

Abstract: An integrated circuit comprising a plurality of modules (M1 to M5, CPU) for processing applications, a global memory (GM), which can be shared by said plurality of modules (M1 to M5, CPU), an interconnect means (IM) for interconnecting said modules (M1 to M5, CPU) and said global memory (GM) based on a plurality of communication services (C1, C2) is provided. Said integrated circuit further comprises at least one communication managing unit (CMU) for managing the communication between said plurality of modules (M1 to M5), wherein said communication managing unit (CMU) receives a request for a communication between at least two of said modules (M1 to M5, CPU) and dynamically selects one of said plurality of communication services (C1, C2) as basis for the requested communication between said modules (MI to M5, CPU).

Abstract: A data processor has a cache memory with an associative memory for storing at least a first and second groups of associations between a respective main memory addresses and cache memory locations. At least one cache memory location is dynamically assignable to different ones of the groups for use in associations of the assigned group. When an instruction indicates a main memory address a group is selected group for finding the cache memory location associated with the main memory address. In an embodiment, the processor accesses streams of addresses from iteratively computed main memory addresses. Each stream has its own group of associations of addresses from the stream with cache memory locations assigned to that group. The remaining cache memory locations are accessed with set associative mapping. Thus, cache memory locations can be assigned to different streams on an “as needed” basis and the remaining cache memory locations can be used for non-stream addresses.

Abstract: A data processor has a cache memory with an associative memory for storing at least a first and second groups of associations between a respective main memory addresses and cache memory locations. At least one cache memory location is dynamically assignable to different ones of the groups for use in associations of the assigned group. When an instruction indicates a main memory address a group is selected group for finding the cache memory location associated with the main memory address. In an embodiment, the processor accesses streams of addresses from iteratively computed main memory addresses. Each stream has its own group of associations of addresses from the stream with cache memory locations assigned to that group. The remaining cache memory locations are accessed with set associative mapping. Thus, cache memory locations can be assigned to different streams on an “as needed” basis and the remaining cache memory locations can be used for non-stream addresses.